Unconventional VTC of subthreshold inverter with MFMIS negative capacitance transistor: An analytical modelling framework with implications for ultralow power logic design

Abstract

The present reports an analytical modelling framework to provide insights into subthreshold logic design using Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) Negative Capacitance Field Effect Transistor (NCFET). It is shown that the proposed model is effective in predicting supply voltage (VDD) dependent hysteresis as well as hysteresis-free voltage transfer characteristics (VTC) through the analytically obtained positive (hysteresis-free) and negative (hysteresis) values of gain (-dVO/dVIN) in NCFET based subthreshold inverter. The proposed subthreshold drain current model for NCFET has been extended to obtain closed-form analytical expressions of figures of merit of a subthreshold inverter such as nominal high and low output voltages, threshold logic voltage, and DC gain. The model while successfully capturing characteristics of MFMIS NCFETs is able to predict the occurrence of hysteresis in VTC due to negative differential resistance (NDR) in the output characteristics of NCFET. Results show that an optimally designed MFMIS NCFET based inverter can achieve similar values of DC gain as exhibited by conventional MOSFET at ~×(3 – 6) times lower supply voltages (VDD) along with an improvement in static and dynamic power dissipation. Results showcase an analytical modelling framework and its implications for reducing VDD for ultralow power subthreshold logic design with NCFETs.

Analytical modeling of architecture dependent atypical scaling trends in metal–Hf0.5Zr0.5O2–metal-SiO2–Si negative capacitance transistors

“…The value of the gain exhibited by the CYL MFMIS NCFET inverter is also higher than that exhibited by the DG MFMIS NCFET. However, for T FE = 5 nm and 6 nm, ULP inverters designed with DG and CYL MFMIS NCFETs show hysteresis in the VTC along with steep transition (high gain) due to the dominance of NDR in the output characteristics of MFMIS devices [44,45]. This indicates that a ULP inverter designed with T FE = 5 nm and 6 nm can function as a Schmitt trigger and can be used to suppress external noise in digital circuits [62].…”

“…Substituting ω = 0 or ω = 1 in (1), the Poisson's equation can be reduced to its form for Cartesian (for DG MFMIS NCFET) or CYL (for CYL MFMIS NCFET) coordinates, respectively. Using (a) the parabolic potential approximation in the vertical (or radial) direction in Si film [12] and (b) the L-K model for FE layer at lower currents corresponding to the subthreshold region [45], the potential distribution in the semiconductor is obtained as…”

Investigation on performance degradation due to induced interface trapped charges on HSO based FDSOI NCFET and sustaining it through back-gate bias

“…Although, MFMIS NCFET is superior in comparison with MFIS NCFET, the stabilisation of NC in MFIS NCFET is slightly higher than MFMIS NCFET [27]. This slight variation in stabilisation can be pre-empted by considering a leakagefree MFMIS NCFET [14,19].…”

“…It is worth noting that, some postulations say the nature of NCFET maybe invalid due to obscurity in device physics consideration [4]. But, a proof-of-concept [5] along with the support of extensive analytical and numerical simulation investigations [6][7][8][9][10][11][12][13][14][15][16][17][18] for NCFET contradict this claim. Hence, this is reaffirming that ferroelectric capacitor when operated in linear or hysteresis free region can certainly amplify V GS by virtue of its negative capacitance (NC) property [19].…”

“…With these hypotheses in place, the next course of action is to realize MFMIS NCFET with ferroelectric capacitor gatestacking on baseline-FDSOI (MIS structure) with a widely used and accepted Landau-Khalatnikov (L-K) model under steady-state NC operation [11][12][13][14][15][16][17]. Zirconium doped HfO 2 (HZO) has been a firm choice of thin-film ferroelectric explored for NCFET applications [12,28].…”