The present work investigates key attributes of metal-ferroelectric-metal-insulatorsemiconductor (MFMIS) cylindrical nanowire (NW) transistor through a physics-based analytical model. The proposed NW MFMIS negative capacitance model is developed by solving the baseline short channel NW model coupled with one-dimensional Landau's equation while considering the radial dependency of electric field in the ferroelectric, a key feature for NW architecture. Contrary to the expected behaviour of a short channel MOSFET, the analytical framework successfully captures the unconventional effects such as an increase in the threshold voltage, lowering of subthreshold swing, and a negative value of drain-induced barrier lowering with gate length downscaling in MFMIS cylindrical NW devices. Also, the impact of ferroelectric thickness, spacer induced polarization charge density, remnant polarization and coercive field on the unconventional short channel effects have been examined. The influence of different ferroelectric materials (Al-HfO 2 , Gd-HfO 2 , Y-HfO 2 , and HZO) on the extent of internal amplification has also been investigated. The developed model provides new insights into the functioning and optimization of NW MFMIS architecture for facilitating hysteresis-free high internal voltage amplification with sub-60 mV/decade swing.
Capacitorless dynamic memory (1T-DRAM) operation in a reconfigurable transistor (RFET) is critically governed by different lengths associated with the architecture. These lengths consisting of ungated region (LUG), control gate (LCG), polarity gate (LPG), storage region length (LS), and total length (LT) can be sensitive to the fabrication process, and hence, critical for 1T-DRAM. This work presents an insightful critique of the above mentioned lengths for realising optimal 1T-DRAM performance. It is shown that RFET with highest values of LS/LT and LCG/LT shows good short channel immunity but does not necessarily ensure enhanced 1T-DRAM metrics. Results indicate that for a fixed LT, retention time (RT) can vary over a wide range (550 ms to 8.7 s) depending on the values of LS/LT and LCG/LT, and hence, appropriate optimization is imperative. The work contributes towards better understanding and optimizing LCG/LT to ensure improved 1T-DRAM metrics in terms of enhanced retention (> 64 ms), acceptable sense margin (> 6 µA/µm), current ratio (> 104) with low values of read (2 ns) and write (1 ns) time to further extend multi-functional facets of nanoscale RFETs for memory applications. In addition, the effect of traps, process sensitivity, reduced number of voltage levels, and disturbance caused by shared word line/bit line are also analysed in this work. Results indicate that state ‘0’ of the cell sharing bit line (BL) with the selected cell is strongly affected by BL disturbance. Word line (WL) disturbance primarily impacts state ‘1’ of the cell sharing WL with selected cell (only for write 1 and read operations).
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.