An Insightful Assessment of 1T-DRAM With Misaligned Polarity Gate in RFET

Roy, Arghya Singha; Semwal, Sandeep; Kranti, Abhinav

doi:10.1109/ted.2022.3170284

Cited by 5 publications

(11 citation statements)

References 31 publications

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“…Thus, the hold concentrations (of holes) remains same for hold '1' (H1) and hold '0' (H0). 18) Therefore, the 1T-DRAM memory operation is not possible in the conventional twin gate RFET structure, which is already mentioned in our previous work. However, RFET2 shown in Fig.…”

Section: Architectural Evaluation Of Rfetsmentioning

confidence: 91%

“…The programming of state 1 (W '1') in the device is carried out through the generation of excess holes (n h1 ) in the device by the positive feedback mechanism initiated through impact ionization 16) in RFET1 whereas, in RFET2, W '1' mechanism has been executed through tunneling of holes across the Schottky barrier along with impact ionization. 18) Therefore, a positive PG bias is essential in RFET1 (to enable tunneling of electrons for impact ionization) in contrast to a negative front PG bias in RFET2 (to enable tunneling hole from metal to semiconductor). Excess holes generated in both devices after programming state (W '1') are stored underneath their respective storage regions i.e.…”

Section: T-dram Operationmentioning

confidence: 99%

“…2. (Color online) Possible integration flow for realization of (a) RFET1 and (b) RFET2 structures through well-known fabrication steps [18][19][20][21][22].…”

mentioning

confidence: 99%

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Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

Nirala

Roy

Semwal

et al. 2023

Jpn. J. Appl. Phys.

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High-speed write/read operation and low energy consumption along with a lower footprint are prerequisites for one transistor (1T) embedded DRAM (eDRAM). This work evaluates the suitability of two different reconfigurable transistors (RFET) architectures for implementing 1T-eDRAM based on key metrics such as high-temperature operation, speed, scalability, and energy consumption. Amongst the two topologies, a twin gate RFET (with one control and program gate each on top and bottom gate oxide) is better suited for 1T-eDRAM due to (i) fast write (1 ns) and read (1 ns) operations, (ii) scalability down to a total source-to-drain length of 60 nm, (iii) better sense margin, and (iv) lower energy consumption during write operation. However, RFET topology with two program gates and one control gates (each on top and bottom gate oxide) shows an enhanced retention time but at the expense of higher energy consumption which may be detrimental for energy efficient system-on-chip applications.

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Section: Architectural Evaluation Of Rfetsmentioning

confidence: 91%

Section: T-dram Operationmentioning

confidence: 99%

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Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

Nirala

Roy

Semwal

et al. 2023

Jpn. J. Appl. Phys.

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“…Apart from demonstrating the potential for logic applications with a reduced number of devices, RFET is also a potential candidate for 1T-DRAM [32,33]. The factors which support 1T-DRAM functionality in RFET include (a) intrinsic channel, (b) carrier generation mechanism [11], (c) location of storage region, (d) longer storage region, and (e) CMOS compatible fabrication process.…”

Section: Introductionmentioning

confidence: 99%

“…In our previous work, we have shown the feasibility of 1T-DRAM with both three gated RFET [32], and twin gated RFET [33] technology. Due to the (a) better gate controllability, and (b) location of the storage region, a three gated RFET shows superior performance over the twin gated RFET.…”

Section: Introductionmentioning

confidence: 99%

A critique of length and bias dependent constraints for 1T-DRAM operation through RFET

Nirala¹,

Semwal²,

Kranti³

2022

Semicond. Sci. Technol.

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Capacitorless dynamic memory (1T-DRAM) operation in a reconfigurable transistor (RFET) is critically governed by different lengths associated with the architecture. These lengths consisting of ungated region (LUG), control gate (LCG), polarity gate (LPG), storage region length (LS), and total length (LT) can be sensitive to the fabrication process, and hence, critical for 1T-DRAM. This work presents an insightful critique of the above mentioned lengths for realising optimal 1T-DRAM performance. It is shown that RFET with highest values of LS/LT and LCG/LT shows good short channel immunity but does not necessarily ensure enhanced 1T-DRAM metrics. Results indicate that for a fixed LT, retention time (RT) can vary over a wide range (550 ms to 8.7 s) depending on the values of LS/LT and LCG/LT, and hence, appropriate optimization is imperative. The work contributes towards better understanding and optimizing LCG/LT to ensure improved 1T-DRAM metrics in terms of enhanced retention (> 64 ms), acceptable sense margin (> 6 µA/µm), current ratio (> 104) with low values of read (2 ns) and write (1 ns) time to further extend multi-functional facets of nanoscale RFETs for memory applications. In addition, the effect of traps, process sensitivity, reduced number of voltage levels, and disturbance caused by shared word line/bit line are also analysed in this work. Results indicate that state ‘0’ of the cell sharing bit line (BL) with the selected cell is strongly affected by BL disturbance. Word line (WL) disturbance primarily impacts state ‘1’ of the cell sharing WL with selected cell (only for write 1 and read operations).

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Insights Into Parasitic Capacitance and Reconfigurable FET Architecture for Enhancing Analog/RF Metrics

Deshpande,

Semwal,

Raskin

et al. 2023

IEEE Trans. Electron Devices

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An Insightful Assessment of 1T-DRAM With Misaligned Polarity Gate in RFET

Cited by 5 publications

References 31 publications

Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

A critique of length and bias dependent constraints for 1T-DRAM operation through RFET

Insights Into Parasitic Capacitance and Reconfigurable FET Architecture for Enhancing Analog/RF Metrics

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