Capacitorless dynamic memory (1T-DRAM) operation in a reconfigurable transistor (RFET) is critically governed by different lengths associated with the architecture. These lengths consisting of ungated region (LUG), control gate (LCG), polarity gate (LPG), storage region length (LS), and total length (LT) can be sensitive to the fabrication process, and hence, critical for 1T-DRAM. This work presents an insightful critique of the above mentioned lengths for realising optimal 1T-DRAM performance. It is shown that RFET with highest values of LS/LT and LCG/LT shows good short channel immunity but does not necessarily ensure enhanced 1T-DRAM metrics. Results indicate that for a fixed LT, retention time (RT) can vary over a wide range (550 ms to 8.7 s) depending on the values of LS/LT and LCG/LT, and hence, appropriate optimization is imperative. The work contributes towards better understanding and optimizing LCG/LT to ensure improved 1T-DRAM metrics in terms of enhanced retention (> 64 ms), acceptable sense margin (> 6 µA/µm), current ratio (> 104) with low values of read (2 ns) and write (1 ns) time to further extend multi-functional facets of nanoscale RFETs for memory applications. In addition, the effect of traps, process sensitivity, reduced number of voltage levels, and disturbance caused by shared word line/bit line are also analysed in this work. Results indicate that state ‘0’ of the cell sharing bit line (BL) with the selected cell is strongly affected by BL disturbance. Word line (WL) disturbance primarily impacts state ‘1’ of the cell sharing WL with selected cell (only for write 1 and read operations).
High-speed write/read operation and low energy consumption along with a lower footprint are prerequisites for one transistor (1T) embedded DRAM (eDRAM). This work evaluates the suitability of two different reconfigurable transistors (RFET) architectures for implementing 1T-eDRAM based on key metrics such as high-temperature operation, speed, scalability, and energy consumption. Amongst the two topologies, a twin gate RFET (with one control and program gate each on top and bottom gate oxide) is better suited for 1T-eDRAM due to (i) fast write (1 ns) and read (1 ns) operations, (ii) scalability down to a total source-to-drain length of 60 nm, (iii) better sense margin, and (iv) lower energy consumption during write operation. However, RFET topology with two program gates and one control gates (each on top and bottom gate oxide) shows an enhanced retention time but at the expense of higher energy consumption which may be detrimental for energy efficient system-on-chip applications.
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