Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

Abstract

High-speed write/read operation and low energy consumption along with a lower footprint are prerequisites for one transistor (1T) embedded DRAM (eDRAM). This work evaluates the suitability of two different reconfigurable transistors (RFET) architectures for implementing 1T-eDRAM based on key metrics such as high-temperature operation, speed, scalability, and energy consumption. Amongst the two topologies, a twin gate RFET (with one control and program gate each on top and bottom gate oxide) is better suited for 1T-eDRAM due to (i) fast write (1 ns) and read (1 ns) operations, (ii) scalability down to a total source-to-drain length of 60 nm, (iii) better sense margin, and (iv) lower energy consumption during write operation. However, RFET topology with two program gates and one control gates (each on top and bottom gate oxide) shows an enhanced retention time but at the expense of higher energy consumption which may be detrimental for energy efficient system-on-chip applications.

Complementary Doped Source-Based Reconfigurable Schottky Diode as an Equivalence Logic Gate

“…Various RFETs have been proposed to improve conduction current, improve integration, and simplify processes. − Compared with complementary metal-oxide-semiconductor field-effect transistor (MOSFET) technology, RFET technology has a significant advantage that it can use fewer devices to realize various logic gates. − With the macro background that CMOS technology will reach the physical limit in the next decade, it is increasingly difficult to improve chip performance solely by reducing device size. Therefore, the RFET has become a research hotspot this year. − The common RFET simultaneously forms a Schottky barrier between the source/drain (S/D) electrode and the conduction and valence bands of dopingless semiconductors. − The tunneling effect is generated by adjusting the program gate voltage, then the S/D resistance generated by the Schottky barrier is reduced, and the carrier type gathered in the S/D region is selected by changing the polarity of the voltage; thus, the conduction type of the device is configured. The control gate is used to regulate the formation of carrier channels.…”

“…Therefore, the RFET has become a research hotspot this year. 8 − 10 The common RFET simultaneously forms a Schottky barrier between the source/drain (S/D) electrode and the conduction and valence bands of dopingless semiconductors. 11 − 17 The tunneling effect is generated by adjusting the program gate voltage, then the S/D resistance generated by the Schottky barrier is reduced, and the carrier type gathered in the S/D region is selected by changing the polarity of the voltage; thus, the conduction type of the device is configured.…”