Investigation on performance degradation due to induced interface trapped charges on HSO based FDSOI NCFET and sustaining it through back-gate bias

Abstract

In this article, a variant of doped HfO\textsubscript{2} based ferroelectric capacitor i.e., silicon doped HfO\textsubscript{2} (hafnia-silica / HSO) is investigated for analytical feasibility and viability for negative capacitance FET (NCFET) applications. Investigations are carried out extensively using well calibrated and validated numerical simulations to find out the optimum ferroelectric thickness (t\textsubscript{f}) of HSO thin-film for the NCFET to operate in hysteresis-free regime. The optimized NCFET is then subjected to the variation of back-gate bias (V\textsubscript{B}) to exploit threshold-voltage (V\textsubscript{TH}) shift phenomena might further improve NCFET performance. In continuance, the optimized NCFET has been introduced with interface trap (+N\textsubscript{it}) charges at the oxide-semiconductor interface to emphasize on the reliability deflation caused at process level design. Hence, this has allowed us to concisely observe and analyse performance degradation aspect of the NCFET with numerical simulations. Also, a feasibility to recuperate the degraded performance caused by +N\textsubscript{it} with utilizing -V\textsubscript{B} is carried out. The performance metrics used in the numerical simulation for the evaluation of HSO ferroelectric NCFET are: sub-threshold slope (SS), charge variation with gate-voltage and ferro voltage, surface potential, V\textsubscript{TH}, drain-current and amplification factor.

Estimation of performance degradation due to interface traps in the gate and spacer stack of NC-FinFET

“…The high permittivity (k) of the capacitive (FE) layer creates numerous reliability issues including bias-temperature instability (BTI) [14][15][16], hot-carrier effects [6] etc, due to the distribution of the high electric field across the interfaces. Thus, such appealing NC devices in the current technological world have numerous interfaces to consider, which introduce critical reliability problems and have received very limited attention [6,[14][15][16][17][18][19][20][21][22]. Device reliability and performance degradation of current modern ICs are majorly influenced by (a) the existence of defect densities in the gate oxides such as the dielectric (DE) layer and FE layer, (b) the trapping of charge in the pre-existing vacancy, by filling or unfilling the defect state, and the concentration of trapped charge varying due to bias conditions, thereby making it a time-dependent phenomenon and (c) the complete trapping of this DE charge, also referred to as residual charge, causing long-lasting damage to the device short-channel characteristics [6,[16][17][18].…”

“…However, to the best of our knowledge, the study of interface trap states present at the spacer (underlap) interface is still unexplored. Hence, there is a necessity to examine the reliability of emerging underlap devices like the NC-fin field effect transistors (FinFETs) [17][18][19][20][21][22] in the presence of interface trap states.…”