Analytical modeling of architecture dependent atypical scaling trends in metal–Hf_0.5Zr_0.5O₂–metal-SiO₂–Si negative capacitance transistors

Abstract

In order to better understand the possible improvement through the incorporation of a ferroelectric layer in the gate stack of the nanoscale transistor, this work develops analytical expressions to assess the scalability of cylindrical (CYL) nanowire and planar double gate (DG) metal-ferroelectric-metal-insulator-semiconductor (MFMIS) negative capacitance (NC) transistors. While predicting sub-60 mV/decade subthreshold swing and negative drain induced barrier lowering (DIBL), results indicate that at lower ferroelectric thickness, the performance of NCFET is primarily governed by the electrostatic integrity of baseline transistor i.e. CYL architecture outperforms planar DG NCFET. However, for relatively thicker TFE, the performance of MFMIS NCFET is strongly governed by the ferroelectric coupling, which indicates comparable performance of DG and CYL MFMIS NCFETs. The formalism, while predicting atypical trends, showcases a pragmatic design criterion for achieving sub-60 mV/dec subthreshold swing and DIBL-free characteristics in MFMIS NC transistor.