Two Dimensional Device Simulation and Fabrication of Mesa SOI Vertical Dual Carrier Field Effect Transistor with Effective Channel Length of 30nm for Switching ASIC and SOC

Yang, Ronghua; Li, G.H.; Xu, Yue; Chao, Yi-Ting; Tang, Zifan; Yang, Y.H.; Ma, Bill; Huang, D.H.; Xu, Ping; Shen, Shih-Jye; Lin, Chih-Yang; Wu, Chunlei; Feng, Yan; Han, Dae-Il; Ren, Yubao; Yu, Leung; Cai, I.M.; Tian, Xiong; Ji, Yongsung; Du, Dong; Huang, Chün-chieh

doi:10.1109/icasic.2005.1611500

Cited by 6 publications

(4 citation statements)

References 1 publication

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“…Fabrication of these interfaces can be done using vertical heterostructures. It has resulted in successful fabrication of various devices [21], [24]- [27], [29], [31]- [34].…”

Section: A Device Structurementioning

confidence: 99%

High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor

Asthana

Ghosh

Goswami

et al. 2014

IEEE Trans. Electron Devices

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Tunnel field-effect transistor (TFET) devices are gaining attention because of good scalability and they have very low leakage current. However, they suffer from low ON-current and high threshold voltage. In this paper, we present III-V heterojunctionless TFET (H-JLTFET) for circuit applications. This paper elaborates on interfacing of III-V with group IV semiconductors for heterojunction. Implementing heterojunction and bandgap engineering, we found that devices have significantly improved performance with very high speed even at very low operating voltage. As there is no doping junction present, future scaling could be feasible along with much higher speed of charge carriers than in silicon. GaAs:Si, Si:Si 0.3 Ge 0.7 , Si:InAs, and GaAs:Ge, H-JLTFET interface for 20-nm gate length (EOT = 2 nm) and dielectric, HfO 2 at V GS = 1 V and temperature of 300 K have I ON of 0.02-12.5 mA/µm, I ON /I OFF of 10 5 − 10 12 , and subthreshold swing (average) of 16-74 mV/decade. Index Terms-Gallium arsenide, hetero junctionless tunnel field-effect transistor (H-JLTFET), high-speed devices, indium arsenide, junctionless tunnel field-effect transistor (JLTFET), tunnel field-effect transistor (TFET).

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“…Fabrication of these interfaces can be done using vertical heterostructures. It has resulted in successful fabrication of various devices [21], [24]- [27], [29], [31]- [34].…”

Section: A Device Structurementioning

confidence: 99%

High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor

Asthana

Ghosh

Goswami

et al. 2014

IEEE Trans. Electron Devices

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“…Also, vertical heterostructures could be a viable solution for the fabrication of this device as vertical structures have resulted in the successful fabrication of many devices. [23][24][25][26][27][28][29] We have used HfO 2 as a gate dielectric. It could be fabricated using atomic layer deposition (ALD), and through ALD, surface oxides are largely eliminated.…”

Section: Device and Simulation Conditionsmentioning

confidence: 99%

Improved performance of a junctionless tunnel field effect transistor with a Si and SiGe heterostructure for ultra low power applications

et al. 2015

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“…We had developed the "Vertical Dual Carrier Field Effect Transistor" (VDCFET) in 1999. Sixteen papers had been published, concerning our development work on VDCFET, in Proceedings of international conferences [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16]. A patent was filed in 2000, and it was awarded by the Patent Office of China in 2004 [17].…”

Section: Introductionmentioning

confidence: 99%

Design theory and fabrication process integration of 65nm and 32nm Node Si vertical dual carrier field effect transistor CPU for parallel arrays of computers.

Shen¹,

Xia

Zhang³

et al. 2007

2007 7th International Conference on ASIC

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In this paper, we present the design theory and fabrication process integration of 65nm and 32nm node Si and Si 1-x Ge x Vertical Dual Carrier Field Effect Transistor (VDCFET) CPU for arrays of parallel computers. The design theory includes the design of complementary VDCFETdevices and their high speed circuits. The fabrication process includes molecular beam epitaxy, electron beam lithgraphy, selective ion implantation and shallow trench isolation of "Silicon on Insulator" substrate. The effective channel lengths of 65nm node and 32nm node Si VDCFET have been reduced to 18nm and 9nm respectively.

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Two Dimensional Device Simulation and Fabrication of Mesa SOI Vertical Dual Carrier Field Effect Transistor with Effective Channel Length of 30nm for Switching ASIC and SOC

Cited by 6 publications

References 1 publication

High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor

High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor

Improved performance of a junctionless tunnel field effect transistor with a Si and SiGe heterostructure for ultra low power applications

Design theory and fabrication process integration of 65nm and 32nm Node Si vertical dual carrier field effect transistor CPU for parallel arrays of computers.

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