Tunnel field-effect transistor (TFET) devices are gaining attention because of good scalability and they have very low leakage current. However, they suffer from low ON-current and high threshold voltage. In this paper, we present III-V heterojunctionless TFET (H-JLTFET) for circuit applications. This paper elaborates on interfacing of III-V with group IV semiconductors for heterojunction. Implementing heterojunction and bandgap engineering, we found that devices have significantly improved performance with very high speed even at very low operating voltage. As there is no doping junction present, future scaling could be feasible along with much higher speed of charge carriers than in silicon. GaAs:Si, Si:Si 0.3 Ge 0.7 , Si:InAs, and GaAs:Ge, H-JLTFET interface for 20-nm gate length (EOT = 2 nm) and dielectric, HfO 2 at V GS = 1 V and temperature of 300 K have I ON of 0.02-12.5 mA/µm, I ON /I OFF of 10 5 − 10 12 , and subthreshold swing (average) of 16-74 mV/decade. Index Terms-Gallium arsenide, hetero junctionless tunnel field-effect transistor (H-JLTFET), high-speed devices, indium arsenide, junctionless tunnel field-effect transistor (JLTFET), tunnel field-effect transistor (TFET).

In this paper, we present improved device characteristics of a Junctionless Tunnel Field Effect Transistor (JLTFET) with a Si and SiGe heterostructure.

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