Leakage current reduction in junctionless tunnel FET using a lightly doped source

Basak, Shibir; Asthana, Pranav Kumar; Goswami, Yogesh; Ghosh, Bahniman

doi:10.1007/s00339-014-8935-9

Cited by 26 publications

(14 citation statements)

References 32 publications

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“…However, the ultra-sharp doping concentration gradient in the source/channel and the drain/channel junctions complicates the fabrication process of TFET device in nanometer regime [6,7]. Recently, a junctionless TFET (JLTFET) has been proposed, in which issues caused by ultra-sharp doping concentration gradient in the source/channel and the drain/channel junctions are eliminated [6][7][8][9][10][11][12]. JLTFET is a heavy doped thin film semiconductor, in which the type and level of doping are unchanged throughout the device.…”

Section: Introductionmentioning

confidence: 99%

Investigation of the impact of mole-fraction on the digital benchmarking parameters as well as sensitivity in GaXIn1−XAs/GaYIn1−YSb vertical heterojunctionless tunneling field effect transistor

Rajabi

Vadizadeh

2021

Int. J. Mod. Phys. B

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Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb vertical heterojunctionless tunneling field effect transistor (VHJL-TFET) has been suggested to optimize the digital benchmarking parameters. In the proposed VHJL-TFET with type II heterostructure (i.e., [Formula: see text] and [Formula: see text]), slight changes in gate voltage cause switching from OFF-state to ON-state. As a result, the electrical properties of Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb VHJL-TFET are excellent in the sub-threshold region. The heterostructure with III–V semiconductors in the source-channel region increases the ON-state current ([Formula: see text]) of the VHJL-TFET. Comparing the results of Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb VHJL-TFET with the simulated devices with type I heterostructure (i.e., [Formula: see text] and [Formula: see text]) and type III heterostructure (i.e., [Formula: see text] and [Formula: see text]) shows the improvement by 26% and 15% in the average subthreshold slope (SS). Sensitivity analysis for VHJL-TFET with the type II heterostructure shows that the sensitivity of OFF-state current ([Formula: see text] to the body thickness ([Formula: see text] and doping concentration ([Formula: see text] is more than the sensitivity of the other main electrical parameters. The Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb VHJL-TFET with a channel length of 20 nm, [Formula: see text] nm, and [Formula: see text] cm[Formula: see text] showed the [Formula: see text] mV/dec, [Formula: see text]/[Formula: see text], and [Formula: see text] mA/um. As a result, Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb VHJL-TFET can be a reasonable choice for digital applications.

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Section: Introductionmentioning

confidence: 99%

Investigation of the impact of mole-fraction on the digital benchmarking parameters as well as sensitivity in GaXIn1−XAs/GaYIn1−YSb vertical heterojunctionless tunneling field effect transistor

Rajabi

Vadizadeh

2021

Int. J. Mod. Phys. B

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“…To avoid complex fabrication processes and high thermal budgets in TFETs, the junctionless tunneling field effect transistor (JLTFET) [22][23][24][25][26][27][28][29][30] has been studied extensively in recent years, which uses uniformly high-doping concentration in the source, channel and drain regions so that the doping concentration and type of channel region are consistent with source region and drain region. Due to uniform doping, the JLTFET is immune to random dopant fluctuations (RDFs) and overcomes complex fabrication processes in manufacturing, meanwhile, source and drain region are formed by the charge plasma concept which further avoids high thermal budgets in the JLTFET.…”

Section: Introductionmentioning

confidence: 99%

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

et al. 2019

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This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 < ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

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“…To avoid the above issues in TFETs, the junctionless tunneling field effect transistor (JLTFET) [24][25][26][27][28][29][30] is proposed, which uses a uniformly high-doping concentration in source, channel, and drain region, wherein the doping concentration and type of channel are consistent with source and drain. Therefore, junctionless tunnel field-effect transistor (JLTFET) is immune to random dopant fluctuations (RDFs) [31], while complex fabrication processes and high thermal budgets in JLTFET manufacturing can be effectively avoided by the charge plasma concept.…”

Section: Introductionmentioning

confidence: 99%

Improvement of Electrical Performance in Heterostructure Junctionless TFET Based on Dual Material Gate

et al. 2019

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In this paper, a dual metallic material gate heterostructure junctionless tunnel field-effect transistor (DMMG-HJLTFET) is proposed and investigated. We use the Si/SiGe heterostructure at the source/channel interface to improve the band to band tunneling (BTBT) rate, and introduce a sandwich stack (GaAs/Si/GaAs) at the drain region to suppress the OFF-state current and ambiplolar current. Simultaneously, to further decrease ambipolar current, the gate electrode is divided into three parts namely auxiliary gate (M1), control gate (M2), and tunnel gate (M3) with workfunctions Φ M1 , Φ M2 and Φ M3 , respectively, where Φ M1 = Φ M3 < Φ M2 . Simulation results indicate that DMMG-HJLTFET provides superior performance in terms of logic and analog/RF as compared with other possible combinations, the ON-state current of the DMMG-HJLTFET increases up to 9.04 × 10 −6 A/µm, and the maximum g m (which determine the analog performance of devices) of DMMG-HJLTFET is 1.11 × 10 −5 S/µm at 1.0V drain-to-source voltage (Vds). Meanwhile, RF performance of devices depends on the cut-off frequency (f T ) and gain bandwidth (GBW), and DMMG-HJLTFET could achieve a maximum f T of 5.84 GHz, and a maximum GBW of 0.39 GHz, respectively.

show abstract

Leakage current reduction in junctionless tunnel FET using a lightly doped source

Cited by 26 publications

References 32 publications

Investigation of the impact of mole-fraction on the digital benchmarking parameters as well as sensitivity in GaXIn1−XAs/GaYIn1−YSb vertical heterojunctionless tunneling field effect transistor

Investigation of the impact of mole-fraction on the digital benchmarking parameters as well as sensitivity in GaXIn1−XAs/GaYIn1−YSb vertical heterojunctionless tunneling field effect transistor

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

Improvement of Electrical Performance in Heterostructure Junctionless TFET Based on Dual Material Gate

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