Design theory and fabrication process integration of 65nm and 32nm Node Si vertical dual carrier field effect transistor CPU for parallel arrays of computers.

Abstract

In this paper, we present the design theory and fabrication process integration of 65nm and 32nm node Si and Si 1-x Ge x Vertical Dual Carrier Field Effect Transistor (VDCFET) CPU for arrays of parallel computers. The design theory includes the design of complementary VDCFETdevices and their high speed circuits. The fabrication process includes molecular beam epitaxy, electron beam lithgraphy, selective ion implantation and shallow trench isolation of "Silicon on Insulator" substrate. The effective channel lengths of 65nm node and 32nm node Si VDCFET have been reduced to 18nm and 9nm respectively.