Turbo decoding on tailored OpenCL processor

Kultala, Heikki; Esko, Otto; Jääskeläinen, Pekka; Guzma, Vladimir; Takala, Jarmo; Jiao, Xianjun; Zetterman, Tommi; Berg, Heikki

doi:10.1109/iwcmc.2013.6583710

Cited by 8 publications

(7 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The Fast configuration, introduced in [13], provides clustered TTA-based processors that can reach high-frequency with large potential of parallel computing. We assume that a chip composed of Fast TTA processors can reach 1GHz using 40nm CMOS technology such as demonstrated in previous work [18].…”

Section: Processor Architecturementioning

confidence: 99%

“…We assume that such platforms can be clocked at 1GHz. Indeed, previous work has shown that the processor cores can already reach 1GHz using 40nm technology [18]. Thus, the results are obtained from a simulated execution, but let us point out that successful implementations of the MPEG-4 Visual decoder has already been synthesized on two different FPGA boards clocked at 100MHz: Altera Stratix III and Xilinx Virtex 6.…”

Section: Analysis Of Performancementioning

confidence: 99%

See 1 more Smart Citation

Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs

Yviquel

Sanchez²,

Jääskeläinen³

et al. 2014

J Sign Process Syst

Self Cite

View full text Add to dashboard Cite

Multimedia applications and embedded platforms are both becoming very complex in order to improve user experience. Thus, multimedia developers need high-level methods to automate time-consuming and error-prone tasks. Dynamic dataflow modeling is attractive to describe complex applications, such as video codecs, at a high level of abstraction. This paper presents a dataflow-based design approach to implement video codecs on embedded multi-core platforms. First, we introduce a custom architecture model to design lowpower multi-core chips based on distributed memory and Transport-Triggered Architecture processor cores. Then, we describe software synthesis techniques to improve dynamic dataflow implementations. This methodology has been implemented into open-source tools and demonstrated on video decoders based on the MPEG-4 Visual standard and the new High Efficiency Video Coding standard. The simulations achieve real-time decoding (40FPS) of high definition (720P) MPEG-4 Visual video sequences on a custom multi-core platformWe would like to thank the organizations which have partially funded this work such as the Center for International Mobility (CIMO) and the Academy of Finland (funding decision 253087). We would also give special thanks to the Orcc and TCE communities as a whole for actively participating in the development of the tools which offers solid basements to this work. clocked at 1Ghz, which is an improvement of more than 100% over previously proposed implementations.

show abstract

Section: Processor Architecturementioning

confidence: 99%

Section: Analysis Of Performancementioning

confidence: 99%

Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs

Yviquel

Sanchez²,

Jääskeläinen³

et al. 2014

J Sign Process Syst

Self Cite

View full text Add to dashboard Cite

show abstract

“…In the past, vector TTA processors used interleaved memory, which increases latency and hardware complexity [4,13]. We have found that many signal processing applications can be written to use linear memory access, so the wide 256-bit data words of our simpler memory hierarchy are a fast and cost-effective solution.…”

Section: Symmetric Clusters For Parallel Codementioning

confidence: 99%

“…In past designs, it was assumed that a PCI Express bus could transport data to an applications processor when sequential execution was necessary [4]. In our previous work, we have found that transferring data between parallel and sequential processors was a significant bottleneck, particularly in heterogeneous CPU and GPU systems [6,14].…”

Section: Main Processor For Sequential Codementioning

confidence: 99%

“…We desire to use flexible LDPC encoding on battery-powered platforms transmitting a large amount of data wirelessly, such as portable medical imaging devices. TTA architectures have already been designed for FEC decoding, but for our application data transmission takes precedence over reception, and flexibility poses a more challenging encoding problem [4,5]. FEC schemes are usually implemented with fixed-function hardware accelerators, but this results in slow time-to-market, inflexible designs, and may consume a large area when many different accelerators are needed on the same platform.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding

Rister

Jääskeläinen

Silvén

et al. 2014

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

Self Cite

View full text Add to dashboard Cite

Exposed-datapath architectures yield small, low-power processors that trade instruction word length for aggressive compile-time scheduling and a high degree of instructionlevel parallelism. In this paper, we present a general-purpose parallel accelerator consisting of a main processor and eight symmetric clusters, all in a single core. Use of a lightweight and memory-efficient application programming interface allows for the first high-performance program executing both sequential and data-parallel code on the same TTA processor. We use the processor for LDPC encoding, a popular method of forward error correction. Demonstrating the flexibility of software-defined radio, we benchmark the processor with two programs, one which can handle almost any sort of LDPC code, and another which is optimized for a specific standard. We achieve a throughput of 5 Mb/s with the flexible program and 92 Mb/s with the standard-specific one, while consuming only 95 mW at a clock frequency of 1175 MHz.

show abstract