The increased performance from technology scaling makes it feasible to operate digital circuits at ultra-low voltages without the significant performance limitation of earlier process generations. The theoretical minimum energy point resides in near-threshold voltages in current processes, but device and environment variations make it a challenge to operate the circuits reliably. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS employing timing-error prevention with clock stretching to enable it to operate with minimal safety margins while maximizing energy efficiency. Measurements show 3.15pJ/cyc energy consumption at 400mV/2.4MHz, which corresponds to 39% energy savings and 83% EDP reduction compared to operation based on static signoff timing.
I. INTRODUCTIONTechnology scaling has traditionally enabled circuits to operate at better energy efficiency than the previous generation. While this still holds true for high-performance circuits operating near the nominal supply voltage, the increased proportion of leakage power has become a limiting factor in energy reduction for systems employing low supply voltage. As pointed in [1], recent manufacturing processes require custom-tailored standard cells to operate efficiently and reliably near the minimum energy point (MEP), where process and environment variations have great impact.In this paper, we show a method of operating logic reliably at the MEP using standard cells from the silicon provider, removing much of the overhead of custom cell design. We have implemented a 32-bit RISC CPU in 28nm CMOS, which has its energy-optimal point at near-threshold supply voltage. To minimize energy-consuming safety margins, we have utilized timing-error prevention (TEP) with adaptive clocking. TEP is a version of timing-error detection (TED) [2] [3] which has been shown to be effective in largely removing variation-incurred timing margins. The TED methodology is based on having the system operate at a voltage and frequency point in which the timing of critical paths fails intermittently. These failed timing occurrences are detected and handled (by instruction replay, etc.), whereas TEP uses adaptive margining to prevent the errors, thereby simplifying the handling process.TEP methodology and its integration to our design is elaborated in Section II. In Section III, we present system simulations which demonstrate the benefits of TEP. Finally, test chip measurements are presented in Section IV.
Two multi-parameter distributions, namely the Pearson type IV and metalog distributions, are discussed and suggested as alternatives to the normal distribution for modelling path delay data that determines the maximum clock frequency (FMAX) of a microprocessor or other digital circuit. These distributions outperform the normal distribution in goodness-of-fit statistics for simulated path delay data derived from a fabricated microcontroller, with the six-term metalog distribution offering the best fit. Furthermore, 99.7% confidence intervals are calculated for some extreme quantiles on each dataset using the previous distributions. Considering the six-term metalog distribution estimates as the golden standard, the relative errors in single paths vary between 4 and 14% for the normal distribution. Finally, the within-die (WID) variation maximum critical path delay distribution for multiple critical paths is derived under the assumption of independence between the paths. Its density function is then used to compute different maximum delays for varying numbers of critical paths, assuming each path has one of the previous distributions with the metalog estimates as the golden standard. For 100 paths, the relative errors are at most 14% for the normal distribution. With 1000 and 10,000 paths, the corresponding errors extend up to 16 and 19%, respectively.
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