Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs

Yviquel, Hervé; Sanchez, Alexandre; Jääskeläinen, Pekka; Takala, Jarmo; Raulet, Mickaël; Casseau, Emmanuel

doi:10.1007/s11265-014-0953-5

Cited by 20 publications

(22 citation statements)

References 27 publications

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“…Hence, it is ideal for validating the partitioning algorithm at the first stage, where communication cost is not yet taken into account. For the experiments presented in this paper, profiling for execution time takes place on the cycle-accurate TTA simulator [15], where the application is executed one actor at a time, on a single processor core. This execution uses an input data for each input buffer of the actor that is currently in execution.…”

Section: Tta Architecture and Profilingmentioning

confidence: 99%

A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures

Michalska¹,

Boutellier²,

Mattavelli³

2015

Procedia Computer Science

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Maximizing the data throughput is a very common implementation objective for several streaming applications. Such task is particularly challenging for implementations based on many-core and multi-core target platforms because, in general, it implies tackling several NPcomplete combinatorial problems. Moreover, an efficient design space exploration requires an accurate evaluation on the basis of dataflow program execution profiling. The focus of the paper is on the methodology challenges for obtaining accurate profiling measures. Experimental results validate a many-core platform built by an array of Transport Triggered Architecture processors for exploring the partitioning search space based on the execution trace analysis.

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Section: Tta Architecture and Profilingmentioning

confidence: 99%

A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures

Michalska¹,

Boutellier²,

Mattavelli³

2015

Procedia Computer Science

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“…The video decoders have been used in many studies and detailed descriptions of them can be found e.g. in [8] and [26]. Table 2 summarizes characteristics of the test case applications.…”

Section: Resultsmentioning

confidence: 99%

Toward Efficient Execution of RVC-CAL Dataflow Programs on Multicore Platforms

Hautala

Boutellier

Nylanden

et al. 2018

J Sign Process Syst

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The increasing number of cores in System on Chips (SoC) has introduced challenges in software parallelization. As an answer to this, the dataflow programming model offers a concurrent and reusability promoting approach for describing applications. In this work, a runtime for executing Dataflow Process Networks (DPN) on multicore platforms is proposed. The main difference between this work and existing methods is letting the operating system perform Central processing unit (CPU) load-balancing freely, instead of limiting thread migration between processing cores through CPU affinity. The proposed runtime is benchmarked on desktop and server multicore platforms using five different applications from video coding and telecommunication domains. The results show that the proposed method offers significant improvements over the stateof-art, in terms of performance and reliability.

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“…Orcc applications are written using the RVC-CAL language, to be translated to software and hardware code. By using Orcc, various video coding applications such as High Efficiency Video Coding have been implemented for various target platforms [21] [22] [23].…”

Section: Related Workmentioning

confidence: 99%

TTADF: Power Efficient Dataflow-Based Multicore Co-Design Flow

Hautala

Boutellier

Silvén

2020

IEEE Trans. Comput.

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The era of mobile communications and the Internet of Things (IoT) has introduced numerous challenges for mobile processing platforms that are responsible for increasingly complex signal processing tasks from different application domains. In recent years, the power efficiency of computing has been improved by adding more parallelism and workload-specific computing resources to such platforms. However, programming of parallel systems can be time-consuming and challenging if only low-level programming methods are used. This work presents a dataflow-based co-design framework TTADF that reduces the design effort of both software and hardware design for mobile processing platforms. The paper presents three application examples from the fields of video coding, machine vision, and wireless communications. The application examples are mapped and profiled both on a pipelined and a shared-memory multicore platform that is generated by TTADF. The results of the TTADF co-design-based solutions are compared against previous manually created designs and a recent dataflow-based design flow, showing that TTADF provides very high energy efficiency together with a high level of automation in software and hardware design.

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Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs

Cited by 20 publications

References 27 publications

A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures

A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures

Toward Efficient Execution of RVC-CAL Dataflow Programs on Multicore Platforms

TTADF: Power Efficient Dataflow-Based Multicore Co-Design Flow

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