Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding

Abstract

Exposed-datapath architectures yield small, low-power processors that trade instruction word length for aggressive compile-time scheduling and a high degree of instructionlevel parallelism. In this paper, we present a general-purpose parallel accelerator consisting of a main processor and eight symmetric clusters, all in a single core. Use of a lightweight and memory-efficient application programming interface allows for the first high-performance program executing both sequential and data-parallel code on the same TTA processor. We use the processor for LDPC encoding, a popular method of forward error correction. Demonstrating the flexibility of software-defined radio, we benchmark the processor with two programs, one which can handle almost any sort of LDPC code, and another which is optimized for a specific standard. We achieve a throughput of 5 Mb/s with the flexible program and 92 Mb/s with the standard-specific one, while consuming only 95 mW at a clock frequency of 1175 MHz.

Transport Triggered Polar Decoders

“…Among other features, it enables direct data transactions between the memory and the functional units, thus alleviating the cost of memory data transfers. TTA processors have been customized for LDPC [9] and Turbocodes [10] but, to the best of our knowledge, this paper reports the first TTA processor specialized for polar decoding. In order to show the modularity of the TTA model, two transport triggered (TT) architectures were designed, the first one is designed for efficient SC decoding (TT-SC), while the second one also supports Soft CANcellation (SCAN) decoding (TT-SCAN).…”