Top-Down Fabricated Reconfigurable FET With Two Symmetric and High-Current On-States

Simon, Maik; Liang, B.; Fischer, D.; Knaut, Martin; Tahn, Alexander; Mikolajick, Thomas; Weber, Walter M.

doi:10.1109/led.2020.2997319

Cited by 41 publications

(29 citation statements)

References 36 publications

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“…[31] Further, the gate and Schottky contact metal work functions and the oxide-induced compressive stress to the Schottky junction could be adjusted to lift the asymmetry of the injection barriers for holes and electrons. [13] Importantly, the possibility of changing the configuration of each transistor within a circuit enables a reconfiguration of its specific logic functions during operation. [32] Further, the bidirectional nature of reconfigurable transistors is a clear advantage for flexible and adaptive circuit design, as equivalent results can be obtained by swapping the signals between source/drain and V PG /V CG .…”

Section: Resultsmentioning

confidence: 99%

“…With the use of Si channels and Ni x Si 1-x contacts various concepts with two or more independent gates have been proven experimentally. [8][9][10][11] Remarkably, symmetry in the output characteristics of p-and n-operation has been reached by the use of strain engineering both on bottom-up [12] and top-down Si nanowire RFETs [13] . Despite those outstanding efforts it has been noted, that the enhancement of the drive current and the reduction of dynamic power consumption strongly scales with the reduction of the respective Schottky barrier heights for electrons and holes.…”

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confidence: 99%

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A Top‐Down Platform Enabling Ge Based Reconfigurable Transistors

Böckle

Sistani

Lipovec

et al. 2021

Adv Materials Technologies

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A popular approach to overcome this limitation is the course-grain reconfiguration, i.e. the signal routing to predefined logic blocks as practiced in field programmable gate arrays (FPGA). [1] This approach nevertheless leads to a high latency in data transfer and substantial chip area consumption since few active regions are not utilized at once. Distinctly, the ansatz of reconfiguration of elementary function blocks, i.e. the fine-grain reconfiguration, gives rise to a paradigm change where devices and circuits are actively redesigned after manufacturing and noteworthy even at runtime. Thereto, combinational circuits have shown benefits in area and power consumption by reconfiguration of complete logic blocks. [2] The building blocks for such circuits are RFETs, capable of merging the electrical properties of unipolar p-and n-type FETs into a single type of device with identical technology, geometry and composition. [3][4][5] Notably, RFETs do not require doping in contrast to classical FETs. Thereto, a device layout with independent gates is used to induce an additional energy barrier to the channel that blocks the undesired charge carrier type and therefore favors p-or n-type operation respectively. Consequently, reducing the technological fabrication complexity, they enable dynamic programming of circuits at the device level. [3,5] Prominent applications of such RFET devices are currently arising in the area of hardware security [6] and in highly integrated combinational and sequential logic. [5,7] Different channel materials have been employed to realize RFETs. With the use of Si channels and Ni x Si 1-x contacts various concepts with two or more independent gates have been proven experimentally. [8][9][10][11] Remarkably, symmetry in the output characteristics of p-and n-operation has been reached by the use of strain engineering both on bottom-up [12] and top-down Si nanowire RFETs [13] . Despite those outstanding efforts it has been noted, that the enhancement of the drive current and the reduction of dynamic power consumption strongly scales with the reduction of the respective Schottky barrier heights for electrons and holes. In this sense, Ge and SiGe have been identified as promising channel materials due to their reduced bandgap compared to the one of Si. Since the highest fraction of transport relevant for device and circuit performance is dictated by quantum mechanical tunneling of charge carriers [12] the use of Ge and Si x Ge 1-x channels Conventional field-effect transistor (FET) concepts are limited to static electrical functions and demand extraordinarily steep and reproducible doping concentration gradients. Reaching the physical limits of scaling, doping-free reconfigurable field-effect transistors (RFETs) capable of dynamically altering the device operation between p-or n-type, even during runtime, are emerging device concepts. In this respect, Ge has been identified as a promising channel material to enable reduction of power consumption and switching delay of RFETs. Nevertheless, its us...

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Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

A Top‐Down Platform Enabling Ge Based Reconfigurable Transistors

Böckle

Sistani

Lipovec

et al. 2021

Adv Materials Technologies

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“…This is particularly detrimental to the PGAS mode, leading to a complete loss of noise margin. However, concerning the PGAD mode, it has been shown that highly scaled devices with a short screening length λ (representing the characteristic length on which potential variations are being screened [19], [20]) can also exhibit a linear output characteristic at room temperature due to the strongly increased tunneling probability through the Schottky barrier [8], [21].…”

Section: Device Characterizationmentioning

confidence: 99%

“…Recently, reconfigurable field-effect transistors (RFETs) have attracted increasing attention because they utilize electrostatic doping to create virtual n-/p-regions avoiding dopant-related issues. Moreover, they can be tuned to operate as n-/p-transistors with unipolar device operation similar to conventional MOSFETs [4]- [8]. Previous work using trigates [4], [5], i.e., two gates for creating virtual source/drain regions and the third one for ON/OFF switching, has demonstrated reconfigurable devices with high I ON /I OFF ratio and steep switching behavior.…”

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confidence: 99%

“…The adoption of three gates will certainly need more space and might become a key limiting factor for downscaling. Hence, devices using only a dual-gate architecture have been investigated [6]- [8] and the impact of process fluctuations in device fabrication has been studied [9]. In these devices, typically, the gate at the drain side is used to 'program' the device either to n-or p-type configuration, while the gate at the source side is used as the switching or control gate.…”

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On the Operation Modes of Dual-Gate Reconfigurable Nanowire Transistors

Sun

Richstein

Liebisch

et al. 2021

IEEE Trans. Electron Devices

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We investigate the operation modes of a dual-gate reconfigurable field-effect transistor (RFET). To this end, dual-gate silicon-nanowire FETs are fabricated based on anisotropic wet etching of silicon and nickel silicidation yielding silicide-nanowire Schottky junctions at source and drain. We compare the program gate at source (PGAS) with the more usual program gate at drain (PGAD) operation mode. While in PGAD mode, ambipolar operation is suppressed, switching is deteriorated due to the injection through a Schottky barrier. Operating the RFET in PGAS mode yields a switching behavior close to a conventional MOSFET. This, however, needs to be traded off against strongly nonlinear output characteristics for small bias voltages. Our measurement results are supported by transport simulations employing a nonequilibrium Green's function approach.

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Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Böckle

Sistani

Bažíková

et al. 2022

Adv Elect Materials

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Modern society is highly depending and relying on electronic computing devices, as for example, employed in efficient servers, personal computers, and mobiles, and currently being explored toward the realization of emerging computing paradigms, such as "artificial intelligence" and the "Internet of Things". [1] A key enabler for these paradigms is the complementary metal-oxide-semiconductor (CMOS) technology, which utilizes the concept of complementary n-and p-type field-effect transistors (FET) to construct Boolean logic gates. Importantly, in CMOS technology the logic functions are fixed by the physical layout of interconnects and the definition of doped regions and thus do not allow for a flexible alteration of the circuits after production. The continuous shrinking of feature sizes of these Si metal-oxide-semiconductor field-effect transistors (MOSFETs) has been providing performance enhancement and higher power efficiency throughout the last decades. However, classical scalability is limited [2] and the static nature of the MOSFET primitives was not developed to provide runtimeadaptability as required for new circuit paradigms. A concept to overcome the static nature in CMOS technology and reduce overall circuit area and power consumption are reconfigurable FETs (RFETs), [3][4][5] encompassing a broad family of devices that enable a reconfiguration of the dominant carrier type based on either Schottky-barrier field-effect transistors (SBFET), [4,[6][7][8][9] or steep slope band-to-band tunneling transistors (TFET), [10][11][12][13] capable of dynamically altering the device operation between n-and p-type. This device concept thus gives rise to a paradigm change where devices, circuits, and even systems are actively and dynamically reconfigured after manufacturing or, as particularly noteworthy, even during run-time, enabling an adaption to the needed logic function of a circuit. Importantly, this "fine-grain" approach is fundamentally different to the already available "coarse-grain" approach followed in field programmable gate arrays (FPGAs) [14] based on signal routing to predefined logic blocks, resulting in high latency in data Metal-semiconductor heterostructures providing geometrically reproducible and abrupt Schottky nanojunctions are highly anticipated for the realization of emerging electronic technologies. This specifically holds for reconfigurable field-effect transistors, capable of dynamically altering the operation mode between n-or p-type even during run-time. Targeting the enhancement of fabrication reproducibility and electrical balancing between operation modes, here a nanoscale Al-Si-Al nanowire heterostructure with single elementary, monocrystalline Al leads and sharp Schottky junctions is implemented. Utilizing a three top-gate architecture, reconfiguration on transistor level is enabled. Having devised symmetric on-currents as well as threshold voltages for n-and p-type operation as a necessary requirement to exploit complementary reconfigurable circuits, selected implementations of log...

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Top-Down Fabricated Reconfigurable FET With Two Symmetric and High-Current On-States

Cited by 41 publications

References 36 publications

A Top‐Down Platform Enabling Ge Based Reconfigurable Transistors

A Top‐Down Platform Enabling Ge Based Reconfigurable Transistors

On the Operation Modes of Dual-Gate Reconfigurable Nanowire Transistors

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

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