Timing optimization for multi-level combinational networks

Chen, Kuang-Chien; Muroga, Saburo

doi:10.1145/123186.105253

Cited by 30 publications

(15 citation statements)

References 15 publications

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“…A decomposition-based technique using partial collapsing and simplification of nodes to reduce the delay is proposed in [5]. The technique proposed in [6] uses permissible functions to resynthesize sets of nodes that lie on the critical path to reduce the delay. In [7], additional redundant circuitry is added to compute the output on input patterns that sensitize the critical paths.…”

Section: Timing-driven Decompositionmentioning

confidence: 99%

“…Timing-driven optimization during multi-level logic synthesis is a well-researched area, and several solutions have been proposed in literature [1][2][3][4][5][6][7][8][9]. These techniques either restructure the critical paths or perform decomposition-based resynthesis of the circuit.…”

Section: Introductionmentioning

confidence: 99%

“…Restructuring techniques, such as [1][2][3][4], are computationally efficient but the improvements from these techniques are limited because restructuring is restricted to cutsets of nodes on the critical path. On the other hand, decomposition-based resynthesis techniques, such as [5][6][7], have immense scope for optimization because the space of possible transformations is vast. However, the algorithms proposed in literature are computationally intensive and the improvements achieved are limited by available computational resources.…”

Section: Introductionmentioning

confidence: 99%

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Timing-driven optimization using lookahead logic circuits

Choudhury

Mohanram

2009

Proceedings of the 46th Annual Design Automation Conference

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This paper describes a timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the parallel prefix problem, the proposed timing-driven optimization produces logic circuits with "lookahead" properties due to the inherent parallelism among the synthesized sub-circuits. Lookahead logic circuits are synthesized using global critical path sensitization information to decompose and reduce the Boolean functions of the nodes in the technology-independent representation of the logic circuit. Unlike prior timing-driven optimization techniques, where synthesis of the decomposition functions is potentially expensive, the proposed technique has the advantage that the decomposition functions are discovered in the synthesized form. On average, the proposed technique reduces the number of logic levels (mapped delay) of 15 benchmark circuits by 40%, 56%, and 22% (21%, 56% and 10%) over the best results of SIS, ABC, and an industrystandard synthesizer, respectively.

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Section: Timing-driven Decompositionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Timing-driven optimization using lookahead logic circuits

Choudhury

Mohanram

2009

Proceedings of the 46th Annual Design Automation Conference

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“…This problem is specially important for timing optimization in which logic restructuring must be performed guided by the critical paths that traverse the entire circuit from inputs to outputs. Different approaches have been developed for timing optimization [9][10][11][12][13]. However, most of them cannot be used in large circuits because of their complexity.…”

Section: Introductionmentioning

confidence: 99%

Dominator-based partitioning for delay optimization

Bañeres

Cortadella

Kishinevsky

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techniques are not always suitable for delay and area logic optimizations. The paper presents an approach that uses a dominator-based partitioning and conventional logic synthesis techniques for delay optimization of large networks. The calculation of dominators is crucial to find topologically ordered clusters suitable for logic restructuring. As a result, a scalable and efficient strategy for delay optimization is proposed and evaluated, showing tangible improvements with respect to existing techniques. A comparison with a standard mincut-based partitioning technique is also presented.

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“…The choice of nodes on which restructuring is applied depends on the maximum delay improvement achievable with minimum area penalty. [16] is another strategy which uses permissible functions and network "don't cares" to optimize the circuit. [1] reduces the delay of the longest sensitizable path in the circuit.…”

mentioning

confidence: 99%

Timing driven gate duplication

Srivastava

Kastner

Chen

et al. 2004

IEEE Trans. VLSI Syst.

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Abstract-In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary inputs(PI) in topologically sorted order evaluating tuples at the input pins of gates. The tuple's first component corresponds to the input pin required time if that gate is not duplicated. The second component corresponds to the input pin required time if that gate were duplicated. After tuple evaluation the algorithm traverses the network from PI to PO in topologically sorted order, deciding the gates to be duplicated. The last and final traversal is again from PO to PI, in which the gates are physically duplicated. Our algorithm uses the dynamic programming structure. We report delay improvements over other optimization methodologies. Gate duplication, along with other optimization strategies, can be used for meeting the stringent delay constraints in today's ultra complex designs.

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Timing optimization for multi-level combinational networks

Cited by 30 publications

References 15 publications

Timing-driven optimization using lookahead logic circuits

Timing-driven optimization using lookahead logic circuits

Dominator-based partitioning for delay optimization

Timing driven gate duplication

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