Timing driven gate duplication

Srivastava, Ankur; Kastner, Ryan; Chen, Chunhong; Sarrafzadeh, Majid

doi:10.1109/tvlsi.2003.820527

Cited by 15 publications

(12 citation statements)

References 27 publications

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“…Table 2 reports the circuit's area increase caused by gate duplication. As reported in [7], gate duplication will increase the area by 8.1% on average. In DUP PREWM, the area penalty gets reduced by up to 5.24% compared to the output of DUP EPSILON .…”

Section: Resultsmentioning

confidence: 87%

“…In this section, we illustrate the proposed CAD tool and algorithm protection approach by developing pre-and post-processing techniques to protect a timing driven gate duplication algorithm [7].…”

Section: Protecting a Gate Duplication Algorithmmentioning

confidence: 99%

“…Recently, Srivastava et al have shown this problem to be NP-Complete and proposed an algorithm DUP EPSILON in the post-technology mapping phase [7]. Their algorithm first traverses the network from primary outputs (PO) to primary inputs (PI) in topologically sorted order, evaluating the following pair at the input pins of each gate: the required times at the input pin if the gate is duplicated; and the ones if the gate is not duplicated.…”

Section: Protecting a Gate Duplication Algorithmmentioning

confidence: 99%

“…To mitigate the area increase due to the duplicated gates, in DUP EPSILON, only gates on non-critical paths are to be considered for duplication. For more details of the algorithm, please refer to paper [7].…”

Section: Protecting a Gate Duplication Algorithmmentioning

confidence: 99%

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VLSI CAD tool protection by birthmarking design solutions

Lin

Srivastava

2005

Proceedings of the 15th ACM Great Lakes Symposium on VLSI

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Many techniques have been proposed in the past for the protection of VLSI design IPs (intellectual property). CAD tools and algorithms are intensively used in all phases of modern VLSI designs; however, little has been done to protect them. Basically, given a problem P and a solution S, we want to be able to determine whether S is obtained by a particular tool or algorithm.We propose two techniques that intentionally leave some trace or birthmark, which refers to certain easy detectable properties, in the design solutions to facilitate CAD tool tracing and protection. The pre-processing technique provides the ideal protection at the cost of losing control of solution's quality. The post-processing technique balances the level of protection and design quality.We conduct a case study on how to protect a timing-driven gate duplication algorithm. Experimental results on a large set of MCNC benchmarks confirm that the pre-processing technique results in a significant reduction (about 48%) of the optimization power of the tool, while the post-processing technique has almost no penalty (less than 2%) on the tool's performance.

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Section: Resultsmentioning

confidence: 87%

Section: Protecting a Gate Duplication Algorithmmentioning

confidence: 99%

Section: Protecting a Gate Duplication Algorithmmentioning

confidence: 99%

Section: Protecting a Gate Duplication Algorithmmentioning

confidence: 99%

See 2 more Smart Citations

VLSI CAD tool protection by birthmarking design solutions

Lin

Srivastava

2005

Proceedings of the 15th ACM Great Lakes Symposium on VLSI

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“…We have integrated these architectures and implementations with novel power aware design methodologies and paradigms for synthesizing highly power optimized implementations. The overall results are given in ref [6] - [25].…”

Section: Power Efficient Architectures For Crypto-algorithmsmentioning

confidence: 99%

Lightweight Cryptographic Techniques

Yuen¹,

Sarrafzadeh²,

Chan³

et al. 2004

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REPORT DOCUMENTATION PAGEForm Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. REPORT TYPE AND DATES COVEREDFinal Jun 02 -Jun 03 TITLE AND SUBTITLELIGHTWEIGHT CRYPTOGRAPHIC TECHNIQUES AUTHOR(S)Horace P. Yuen, Majjid Sarrafzadeh, Agnes Chan, and Aggelos Katsagelos FUNDING NUMBERSC -F30602-00-2-0536 PE -62302E PR -K251 TA -25 WU -A1 PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES)Northwestern University Evanston Illinois 60208-3113 PERFORMING ORGANIZATION REPORT NUMBERN/A SPONSORING / MONITORING AGENCY NAME(S) AND ADDRESS(ES)Defense 12b. DISTRIBUTION CODE ABSTRACT (Maximum 200 Words)The objective of this project was to develop new cryptographic techniques, and to modify the important existing ones, for applications to encryption and authentication in energy-constrained sensors with limited memory and computational capability. The goal was to minimize power consumption in order to maximize the lifetime of the sensor operation and the amount of useful processing that can be carried out within the lifetime. For handling low power stream cipher on small handheld devices, Software Based Stream Ciphers were implemented and compared with other software based encryption algorithms. A new spread signal cryptographic technique has been developed that promises significant additional security with no new bandwidth or power overhead. New design methodologies have been developed for power conscious systems with power/security tradeoffs. The impact of imaging sensors on benchmark and operational scenarios related to target tracking in a wireless sensor network has been investigated in an added task. Leveraging on the state-of-the-art in image-based tracking, new algorithms and novel methods have been discovered that enhance the capability of existing imaging technologies. NUMBER OF PAGES 26

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Physically-Driven Logic Restructuring

Papa

Markov

2012

Lecture Notes in Electrical Engineering

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Timing driven gate duplication

Cited by 15 publications

References 27 publications

VLSI CAD tool protection by birthmarking design solutions

VLSI CAD tool protection by birthmarking design solutions

Lightweight Cryptographic Techniques

Physically-Driven Logic Restructuring

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