Physically-Driven Logic Restructuring

Papa, David A.; Markov, Igor L.

doi:10.1007/978-1-4614-1356-1_6

Cited by 2 publications

(1 citation statement)

References 11 publications

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“…In the conventional CMOS technology, fanout optimization has been well-studied, both as a method to improve the critical path delay [1]- [5] and as a method of optimizing special highfanout nets such as clock and reset signals [6]. However, the techniques developed for CMOS technology are not generally transferable to many emerging technologies such as superconducting electronics (e.g., AQFP [7], RQL [8], RSFQ [9]) and spintronics [10], which generally have tight, explicit fanout bounds and/or significantly different timing models (clocked gates, for example).…”

Section: Introductionmentioning

confidence: 99%

Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach

Marakkalage

Micheli

2023

2023 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In logic circuits, the number of fanouts a gate can drive is limited, and such limits are tighter in emerging technologies such as superconducting electronic circuits. In this work, we study the problem of resynthesizing a logic network with bounded-fanout gates while minimizing area. We 1) formulate this problem for a fixed target logic depth as an integer linear program (ILP) and present exact solutions for small logic networks, and 2) propose a top-down approach to construct a feasible solution to the ILP which yields an efficient algorithm for fanout bounded synthesis. When using the minimum depth achievable with unbounded fanouts as the target logic depth, our top-down approach achieves 11.82% better area as compared to the stateof-the-art with matching or better delays.

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Section: Introductionmentioning

confidence: 99%

Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach

Marakkalage

Micheli

2023

2023 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Fanout-Bounded Logic Synthesis for Emerging Technologies

Marakkalage,

De Micheli

2024

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In logic circuits, the number of fanouts a gate can drive is limited, and such limits are tighter in emerging technologies such as superconducting electronic circuits. Moreover, some such technologies, e.g., adiabatic quantum-flux-parametron (AQFP), pose additional constraints such as the need for balanced input-to-output paths to ensure proper signal propagation. In this work, targeting emerging technologies, we study the problem of re-synthesizing a logic network with bounded-fanout gates while minimizing area for a given depth. Namely, we 1) formulate the fanout-bounded synthesis (FBS) problem for a fixed target logic depth as an integer linear program (ILP), 2) propose a scalable top-down approach to construct a feasible solution to the ILP, and 3) extend both the exact and the heuristic approaches to the setting of path-balanced networks. Using our ILP, we obtain the global optimum solutions for a number of benchmarks that serve as ground truth for evaluating heuristic algorithms in both general and path-balanced FBS. Our heuristic algorithm for general FBS achieves an 11.82% better area than the state of the art with matching or better delays while attaining the optimum/near-optimum area for several considered benchmarks. For the path-balanced setting, our heuristic approach achieves 8.76% better delay on average with an average area improvement of 0.5% when using AQFP as the exemplar technology, while achieving more than 17% better delays on several benchmarks.

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Physically-Driven Logic Restructuring

Cited by 2 publications

References 11 publications

Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach

Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach

Fanout-Bounded Logic Synthesis for Emerging Technologies

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