Timing-driven optimization using lookahead logic circuits

Abstract

This paper describes a timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the parallel prefix problem, the proposed timing-driven optimization produces logic circuits with "lookahead" properties due to the inherent parallelism among the synthesized sub-circuits. Lookahead logic circuits are synthesized using global critical path sensitization information to decompose and reduce the Boolean functions of the nodes in the technology-independent representation of the logic circuit. Unlike prior timing-driven optimization techniques, where synthesis of the decomposition functions is potentially expensive, the proposed technique has the advantage that the decomposition functions are discovered in the synthesized form. On average, the proposed technique reduces the number of logic levels (mapped delay) of 15 benchmark circuits by 40%, 56%, and 22% (21%, 56% and 10%) over the best results of SIS, ABC, and an industrystandard synthesizer, respectively.