Thermal analysis of solid-state devices and circuits: an analytical approach

Rinaldi, N.

doi:10.1016/s0038-1101(00)00120-9

Cited by 55 publications

(26 citation statements)

References 22 publications

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“…In this paper we are only interested in the spatial temperature variations on the chip surface, for which (2) is a good model also used by other authors [14].…”

Section: Model For the Temperature Distributionmentioning

confidence: 99%

Unstable Inverse Heat Transfer Problems in Microelectronics

2013

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Inverse heat transfer problems are very important for the thermal testability of integrated circuits. Temperature sensors integrated on the same chip measure in real time the power dissipation in one or more critical heat sources of the circuit in order to prevent overheating. It will be demonstrated that these kinds of problems can give rise to mathematical unstabilities or the ill conditioning of the inverse problem. This statement will be proved with the help of several particular cases.

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“…In this paper we are only interested in the spatial temperature variations on the chip surface, for which (2) is a good model also used by other authors [14].…”

Section: Model For the Temperature Distributionmentioning

confidence: 99%

Unstable Inverse Heat Transfer Problems in Microelectronics

2013

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“…For these devices, the thermal resistance was estimated as The temperature dependence of silicon thermal conductivity is more important in silicon on insulator (SOI) technologies where self-heating contributes to rise in junction temperature. So, our calculations assumed that the thermal resistance of silicon was temperature independent [17,18]. We used Eq.…”

Section: Semiconductor Thermal Resistance Modelsmentioning

confidence: 99%

Burn-in temperature projections for deep sub-micron technologies

Semenov

Vassighi²,

Sachdev³

et al.

International Test Conference, 2003. Proceedings. ITC 2003.

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Bum-in faces significant challenges in recent CMOS technologies. The self-generated heat of each IC in a burn-in environment contributes to larger currents that can lead to further increase in junction temperatures, possible thermal run away, and yield-loss of good parts. Calculations show that the junction temperature is increasing by 1.45Xlgeneration. This paper estimates the increase in junction temperature with scaling and discusses the optimal burn-in temperature with scaling. Our research indicates that the burn-in temperature must also be reduced with technology scaling. The impact on commercial burn-in ovens is also described.

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“…Recently, a relationship between thermal resistance of a MOSFET and its geometrical parameters was derived using 3-D heat flow equation [7].…”

Section: : Introductionmentioning

confidence: 99%

“…Where K is the thermal conductivity of silicon (K = 1.5 X 10-4HT/J.LmoC [7]), L and W are channel geometry parameters. The thermal conductivity of the silicon exhibits weak temperature dependence described as [8]:…”

Section: : Introductionmentioning

confidence: 99%

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Effect of static power dissipation in burn-in environment on yield of VLSI

Vassighi

Semenov

Sachdev

et al.

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.

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The leakage power is expected to inc ease with scaling of CMOS technology. The increased leakage is a strong function of the elev ted temperature and voltage stress. As a consequence, under the bum-in (BI) conditions the levated leakage power may cause increased post Burnin fallout. In this paper the impact elevated leakage and technology scaling in bum-in environment on post BI yield is analy ed. We have also shown that to maintain a constant post-BI yield loss, the burn-in tempe ature should go down by lO°C for each technology generation. We also show that at stati burn-in conditions, the die temperature is increased exponentially and range of optimal st essed voltage and temperature for fixed post bum-in yield loss is reduced significantly, whe CMOS technology is aggressively scaled down. 1: IntroductionBurn-in (BI) is an important test t chnique to weed out infant mortality from the main population.As a result, quality and eliability of outgoing Integrated Circuits (ICs) are improved. During the BI, ICs are subj cted to elevated voltage and temperature stress. As a consequence, the field and temperat re enhanced failure mechanisms are accelerated [1].Optimization of effectiveness of BI test has been the constant focus of quality and reliability engineers.As we scale the transistor to deep s b-micron regime, it's off state leakage increases significantly. A linear reduction in transis or threshold voltage with technology scaling, results in exponential increase in its leakage. This leakage is further increased under voltage and temperature stress conditions. High 1 akage causes further elevation in chip temperature and eventually leads to a positive feed ack. Therefore, handling the power dissipation, becomes an important consideration duing the burn-in. In this article, we investigate static power dissipation as a function of tern erature and voltage. The objective is to minimize the burn-in temperature and voltage, hile maintaining constant yield during the burn-in test for future technologies.

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Thermal analysis of solid-state devices and circuits: an analytical approach

Cited by 55 publications

References 22 publications

Unstable Inverse Heat Transfer Problems in Microelectronics

Unstable Inverse Heat Transfer Problems in Microelectronics

Burn-in temperature projections for deep sub-micron technologies

Effect of static power dissipation in burn-in environment on yield of VLSI

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