Burn-in temperature projections for deep sub-micron technologies

Semenov, O.; Vassighi, A.; Sachdev, Manoj; Keshavarzi, Ali; Hawkins, C.F.

doi:10.1109/test.2003.1270829

Cited by 14 publications

(8 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Significant power reduction can be obtained if the junction temperature is reduced. This dependence on temperature of leakage power (and hence, of total thermal design power) has serious implications in microprocessor testing and noise immunity [22].…”

Section: Leakage Power: Mechanisms and Trendsmentioning

confidence: 99%

Towards a Thermal Moore's Law

Krishnan

Garimella

Chrysler

et al. 2007

IEEE Trans. Adv. Packag.

128

View full text Add to dashboard Cite

Thermal design power trends and power densities for present and future single-core microprocessors are investigated. These trends are derived based on Moore's law and scaling theory. Both active and stand-by power are discussed and accounted for in the calculations. A brief discussion of various leakage power components and their impact on the power density trends is provided. Two different lower limits of heat dissipation for irreversible logic computers that have previously appeared in the literature are discussed. These are based on the irreversibility of logic to represent one bit of information, and on the distribution of electrons to represent a bit. These limits are found to be two or more orders of magnitude lower than present-day microprocessor thermal design power trends. Further, these thermal demand trends are compared to the projected trends for the desktop product sector from the International Technology Roadmap for Semiconductors (ITRS). To evaluate the thermal impact of projected power densities, heat sink thermal resistances are calculated for a given technology target. Based on the heat sink thermal resistance trends, the evolution of a consistent air-cooling limit is predicted. One viable alternative to air-cooling, i.e., the use of high-efficiency solid-state thermoelectric coolers (TECs), is explored in detail. The impact of different parasitics on the thermoelectric figure of merit (ZT) is quantified.

show abstract

Section: Leakage Power: Mechanisms and Trendsmentioning

confidence: 99%

Towards a Thermal Moore's Law

Krishnan

Garimella

Chrysler

et al. 2007

IEEE Trans. Adv. Packag.

128

View full text Add to dashboard Cite

show abstract

“…This transistor has to dissipate about 6 mW of power (4 mA at 1.5 V). In [17], transistor power dissipation per transistor area has been given at an operating frequency of 1.6 GHz based on TSMC's 0.18 micron process. Assuming the power dissipation per transistor area is approximately at 10.13 lw/ lm 2 , total transistor area can be calculated as 592 lm 2 .…”

Section: The Transmitter or Led Driver Circuitmentioning

confidence: 99%

Avalanche breakdown in silicon devices for contactless logic testing and optical interconnect

Sayıl

2008

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

A silicon p-n junction that is biased in avalanche breakdown mode emits visible light. Although the efficiency of such silicon emitters is poor, their ability to modulate at GHz frequencies make them a good choice for many applications including optical interconnect and optical contactless logic testing. Results demonstrate the feasibility of an all silicon optical interconnect system and an all silicon contactless testing methodology using the silicon light emitter and standard silicon detectors. The development of truly efficient silicon light emitting would enable many new applications.

show abstract

“…For arch2 compared to arch1, there is another energy overhead using a register file with more read/write ports. In 180nm the leakage power is negligible compared to the active power [14], therefore, it has been neglected in our evaluation.…”

Section: •Energy Consumption Evaluationmentioning

confidence: 99%

Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension

Noori¹,

Mehdipour²,

Inoue³

et al. 2008

Proceeding of the Thirteenth International Symposium on Low Power Electronics and Design - ISLPED '08

View full text Add to dashboard Cite

Application-specific instruction set extension is an effective technique for reducing accesses to components such as on-and off-chip memories, register file and enhancing the energy efficiency. However, the addition of custom functional units to the base processor is required for supporting custom instructions, which due to the increase of manufacturing and design costs in new nanometer-scale technologies and shorter time-to-market, is becoming an issue. To address above issues, in our proposed approach, an optimized reconfigurable functional unit is used instead, and instruction set customization is done after chip-fabrication. Therefore, while maintaining the flexibility of a conventional microprocessor, the low-energy feature of customization is applicable. Experimental results show that the maximum and average energy savings are 67% and 22%, respectively for our proposed architecture framework.

show abstract

Burn-in temperature projections for deep sub-micron technologies

Cited by 14 publications

References 28 publications

Towards a Thermal Moore's Law

Towards a Thermal Moore's Law

Avalanche breakdown in silicon devices for contactless logic testing and optical interconnect

Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension

Contact Info

Product

Resources

About