There is a significant need for site-specific and on-demand cooling in electronic, optoelectronic and bioanalytical devices, where cooling is currently achieved by the use of bulky and/or over-designed system-level solutions. Thermoelectric devices can address these limitations while also enabling energy-efficient solutions, and significant progress has been made in the development of nanostructured thermoelectric materials with enhanced figures-of-merit. However, fully functional practical thermoelectric coolers have not been made from these nanomaterials due to the enormous difficulties in integrating nanoscale materials into microscale devices and packaged macroscale systems. Here, we show the integration of thermoelectric coolers fabricated from nanostructured Bi2Te3-based thin-film superlattices into state-of-the-art electronic packages. We report cooling of as much as 15 degrees C at the targeted region on a silicon chip with a high ( approximately 1,300 W cm-2) heat flux. This is the first demonstration of viable chip-scale refrigeration technology and has the potential to enable a wide range of currently thermally limited applications.

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Thermal design power trends and power densities for present and future single-core microprocessors are investigated. These trends are derived based on Moore's law and scaling theory. Both active and stand-by power are discussed and accounted for in the calculations. A brief discussion of various leakage power components and their impact on the power density trends is provided. Two different lower limits of heat dissipation for irreversible logic computers that have previously appeared in the literature are discussed. These are based on the irreversibility of logic to represent one bit of information, and on the distribution of electrons to represent a bit. These limits are found to be two or more orders of magnitude lower than present-day microprocessor thermal design power trends. Further, these thermal demand trends are compared to the projected trends for the desktop product sector from the International Technology Roadmap for Semiconductors (ITRS). To evaluate the thermal impact of projected power densities, heat sink thermal resistances are calculated for a given technology target. Based on the heat sink thermal resistance trends, the evolution of a consistent air-cooling limit is predicted. One viable alternative to air-cooling, i.e., the use of high-efficiency solid-state thermoelectric coolers (TECs), is explored in detail. The impact of different parasitics on the thermoelectric figure of merit (ZT) is quantified.

A three-part study encompassing both experiment and analysis has been performed for natural convection in an open-ended vertical channel. One of the principal walls of the channel—the heated wall—was maintained at a uniform temperature, while the other principal wall was unheated. The experiments, which included flow visualization and Nusselt number measurements, were carried out with water in the channel and in the ambient which surrounds the channel. At Rayleigh numbers which exceeded a threshold value, the visualization revealed a pocket of recirculating flow situated adjacent to the unheated wall in the upper part of the channel. The recirculation was fed by fluid drawn into the top of the channel, adjacent to the unheated wall. Average Nusselt numbers for the heated wall were measured over a three orders of magnitude range of a single correlating parameter, which includes the Rayleigh number and the ratio of the channel length to the interwall spacing. The Nusselt numbers were found to be unaffected by the presence of the recirculation zone. Numerical solutions obtained via a parabolic finite difference scheme yielded Nusselt numbers in good agreement with those of experiment. The numerical results covered the Prandtl number range from 0.7 to 10.

Over the past few years, thermal design for cooling microprocessors has become increasingly challenging mainly because of an increase in both average power density and local power density, commonly referred to as “hot spots”. The current air cooling technologies present diminishing returns, thus it is strategically important for the microelectronics industry to establish the research and development focus for future non air-cooling technologies. This paper presents the thermal performance capability for enabling and package based cooling technologies using a range of “reasonable” boundary conditions. In the enabling area a few key main building blocks are considered: air cooling, high conductivity materials, liquid cooling (single and two-phase), thermoelectric modules integrated with heat pipes/vapor chambers, refrigeration based devices and the thermal interface materials performance. For package based technologies we present only the microchannel building block (cold plate in contact with the back-side of the die). It will be shown that as the hot spot density factor increases, package based cooling technologies should be considered for more significant cooling improvements. In addition to thermal performance, a summary of the key technical challenges are presented in the paper.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.