There is a significant need for site-specific and on-demand cooling in electronic, optoelectronic and bioanalytical devices, where cooling is currently achieved by the use of bulky and/or over-designed system-level solutions. Thermoelectric devices can address these limitations while also enabling energy-efficient solutions, and significant progress has been made in the development of nanostructured thermoelectric materials with enhanced figures-of-merit. However, fully functional practical thermoelectric coolers have not been made from these nanomaterials due to the enormous difficulties in integrating nanoscale materials into microscale devices and packaged macroscale systems. Here, we show the integration of thermoelectric coolers fabricated from nanostructured Bi2Te3-based thin-film superlattices into state-of-the-art electronic packages. We report cooling of as much as 15 degrees C at the targeted region on a silicon chip with a high ( approximately 1,300 W cm-2) heat flux. This is the first demonstration of viable chip-scale refrigeration technology and has the potential to enable a wide range of currently thermally limited applications.

Thermal challenges in next-generation electronic systems, as identified through panel presentations and ensuing discussions at the workshop, Thermal Challenges in Next Generation Electronic Systems, held in Santa Fe, NM, January 7-10, 2007, are summarized in this paper. Diverse topics are covered, including electrothermal and multiphysics codesign of electronics, new and nanostructured materials, high heat flux thermal management, site-specific thermal management, thermal design of next-generation data centers, thermal challenges for military, automotive, and harsh environment electronic systems, progress and challenges in software tools, and advances in measurement and characterization. Barriers to further progress in each area that require the attention of the research community are identified.

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During service, microcracks form inside solder joints, making microelectronic packages highly prone to failure on dropping. Hence, the fracture behavior of solder joints under drop conditions at high strain rates and under mixed-mode conditions is a critically important design consideration for robust joints. This study reports on the effects of joint processing and loading conditions on the microstructure and fracture response of Sn-3.8%Ag-0.7%Cu (SAC387) solder joints attached to Cu substrates. The impact of parameters which control the microstructure (reflow condition, aging) as well as loading conditions (strain rate and loading angle) are explicitly studied. A methodology based on the calculation of the critical energy release rate, G C , using compact mixed-mode (CMM) samples was developed to quantify the fracture toughness of the joints under conditions of adhesive (i.e., interface-related) fracture. In general, higher strain rate and increased mode-mixity resulted in decreased G C . G C also decreased with increasing dwell time at reflow temperature, which produced a thicker intermetallic layer at the solder-substrate interface. Softer solders, produced by slower cooling following reflow, or post-reflow aging, showed enhanced G C . The sensitivity of the fracture toughness to all of the aforementioned parameters reduced with an increase in the mode-mixity. Fracture mechanisms, elucidating the effects of the loading conditions and process parameters, are briefly highlighted.

Thermal design power trends and power densities for present and future single-core microprocessors are investigated. These trends are derived based on Moore's law and scaling theory. Both active and stand-by power are discussed and accounted for in the calculations. A brief discussion of various leakage power components and their impact on the power density trends is provided. Two different lower limits of heat dissipation for irreversible logic computers that have previously appeared in the literature are discussed. These are based on the irreversibility of logic to represent one bit of information, and on the distribution of electrons to represent a bit. These limits are found to be two or more orders of magnitude lower than present-day microprocessor thermal design power trends. Further, these thermal demand trends are compared to the projected trends for the desktop product sector from the International Technology Roadmap for Semiconductors (ITRS). To evaluate the thermal impact of projected power densities, heat sink thermal resistances are calculated for a given technology target. Based on the heat sink thermal resistance trends, the evolution of a consistent air-cooling limit is predicted. One viable alternative to air-cooling, i.e., the use of high-efficiency solid-state thermoelectric coolers (TECs), is explored in detail. The impact of different parasitics on the thermoelectric figure of merit (ZT) is quantified.