There is a significant need for site-specific and on-demand cooling in electronic, optoelectronic and bioanalytical devices, where cooling is currently achieved by the use of bulky and/or over-designed system-level solutions. Thermoelectric devices can address these limitations while also enabling energy-efficient solutions, and significant progress has been made in the development of nanostructured thermoelectric materials with enhanced figures-of-merit. However, fully functional practical thermoelectric coolers have not been made from these nanomaterials due to the enormous difficulties in integrating nanoscale materials into microscale devices and packaged macroscale systems. Here, we show the integration of thermoelectric coolers fabricated from nanostructured Bi2Te3-based thin-film superlattices into state-of-the-art electronic packages. We report cooling of as much as 15 degrees C at the targeted region on a silicon chip with a high ( approximately 1,300 W cm-2) heat flux. This is the first demonstration of viable chip-scale refrigeration technology and has the potential to enable a wide range of currently thermally limited applications.

Thermal conductivity (kappa) of isolated carbon nanotubes (CNTs) is higher than the kappa of diamond; however, in this Letter we show that the kappa of a packed bed of three-dimensional random networks of single and multiwall CNTs is smaller than that of thermally insulating amorphous polymers. The thermoelectric power (Sigma) of the random network of CNTs was also measured. The Sigma of a single wall nanotube network is very similar to that of isolated nanotubes and, in contrast with kappa, Sigma shows a strong dependence on the tube diameter.

We show that thermal conductivity of packed bed of alumina nanoparticles can be as low as 0.035W∕mK which is only 35% higher than the thermal conductivity of air and is smaller than the recently reported lowest thermal conductivity of solids using disordered layered WeS2. These findings show a promising approach for making low-cost and ultralow thermal conductivity thermal insulation materials with high density and good sustainability at high pressures.

Tailoring electrical and thermal contact conductivities (Σc and Γc) across metallized pnictogen chalcogenide interfaces is key for realizing efficient thermoelectric devices. The authors report that Cu, Ni, Ti, and Ta diffusion and interfacial telluride formation with n-Bi2Te3 and p-Sb2Te3 influence both Σc and Γc. Cu metallization yields the highest Γc and the lowest Σc, correlating with maximal metal diffusion and copper telluride formation. Ni diffuses less and yields the highest Σc with Sb2Te3 due to p-type nickel telluride formation, which diminishes Σc improvement with n-Bi2Te3 interfaces. Ta and Ti contacts yield the lowest properties similar to that in Ni-metallized structures. These correlations between interfacial diffusion and phase formation on electronic and thermal transport properties will be important for devising suitable metallization for thermoelectric devices.

We have recently reported the first ever demonstration of active cooling of hot-spots of >1 kW/cm2 in a packaged electronic chip using thin-film superlattice thermoelectric cooler (TEC) cooling technology [1]. In this paper, we provide a detailed account of both experimental and theoretical aspects of this technological demonstration and progress. We have achieved cooling of as much as 15°C at a location on the chip where the heat-flux is as high as ∼1300 W/cm2, with the help of a thin-film TEC integrated into the package. To our knowledge, this is the first demonstration of high heat-flux cooling with a thin-film thermoelectric device made from superlattices when it is fully integrated into a usable electronic package. Our results, which validate the concept of site-specific micro-scale cooling of electronics in general, will have significant potential for thermal management of future generations of microprocessors. Similar active thermal management could also be relevant for high-performance solid-state lasers and power electronic chips.