The role of the Ge mole fraction in improving the performance of a nanoscale junctionless tunneling FET: concept and scaling capability

Ferhati, H.; Djeffal, F.; Bentrcia, Toufik

doi:10.3762/bjnano.9.177

Cited by 24 publications

(3 citation statements)

References 26 publications

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“…The increase in the BTBT generation rate at a higher Ge mf is also evident in figure 7(b). A high Ge mf further changes the threshold voltage to influence the SS value [34]. The Fermi energy level of electrons for varying mf in the ON state was also investigated and is presented in figure 7(c), where it is seen that the Fermi level increases for a corresponding increase in mf.…”

Section: Impact Of Variation In Mole Fractionmentioning

confidence: 99%

Interface trap-induced radiofrequency and low-frequency noise analysis under temperature variation of a heterostacked source L-gate tunnel field effect transistor

Das,

Chakraborty,

Borah

2024

Semicond. Sci. Technol.

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This brief exclusively demonstrates a comprehensive analysis of the adverse impact of interface trap charge (ITC) under the influence of temperature variation on a hetero-stacked (HS) source L-gate tunnel field effect transistor (TFET) having SiGe pocket. An investigation of both static and RF characteristics has been carried out. It appears that ITCs situated at the Silicon (Si)/oxide interface fluctuates the flat-band voltage to alter the various analog/RF parameter characteristics. Uniform ITCs are seen to be less susceptible to degradation in device characteristics. The low frequency noise (LFN) analysis has also been investigated considering the impact of different trap distribution (Uniform and Gaussian) and densities which are compared thereafter. Besides, the temperature dependent LFN has been studied under influence of different distributed ITCs which is rarely explored yet. Moreover, a comparative analysis has been done on the device behaviour and LFN characteristics of HS L-gate TFET structures with and without SiGe pocket. The structure with SiGe pocket is found to be insusceptible to noise effects.

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Section: Impact Of Variation In Mole Fractionmentioning

confidence: 99%

Interface trap-induced radiofrequency and low-frequency noise analysis under temperature variation of a heterostacked source L-gate tunnel field effect transistor

Das,

Chakraborty,

Borah

2024

Semicond. Sci. Technol.

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“…Both the gates are connected to common supply voltage for smooth and equal control over the channel. Furthermore, the metallic gate with work function ϕ m = 4.8 eV is optimized for the OFF-state current along with ON-state current which results in high I ON /I OFF ratio with V gs = 1.0 V, V ds = 1.0 V. [10][11][12][13][14][15] The inner gate oxide and outer gate oxide are also of 1 nm in thickness and HfO 2 is used to further improve the electrical characteristics of device. For the same, a uniform doping profile has been used N d = 1 Â 10 19 cm À3 in all regions like which is irrespective of hetero-interfaces.…”

Section: Device Structure and Design Parametersmentioning

confidence: 99%

Parameteric optimization of SiGe S/D NT JLFET using analytical modeling to improve L‐BTBT induced GIDL

Thakur,

Dhiman,

Wadhwa

et al. 2024

Int J Numerical Modelling

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In the present work, we investigate the impact of structure dimensional parameters on the short channel effects which occurs especially below 20 nm regime particularly gate induced drain leakage (GIDL) current. Using technology computer aided design simulation (TCAD), we have examined the GIDL for SiGe as source/drain in NTJLFET. The structural dimensional parameters such as the nanotube thickness, core and outer gates thickness and gate electrode work function shows the significant impact on the band to band tunneling in lateral direction (L‐BTBT) which induced GIDL current. It is analyzed that increase in the nanotube thickness and physical oxide thickness increase the GIDL current, while increasing the gate electrode work function, core gate and outer gate thicknesses gives reduced GIDL current. The SiGe S/D NTJLFET produce a remarkable high ION/IOFF ratio ~ 1011. A compact model for GIDL current is also developed which shows the dependency of structure parameters on leakage current. The SiGe has been incorporated as source and drain in NTJLFET which creates the energy band discontinuity. Furthermore, SiGe S/D NTJLFET is fairly compared with the conventional NT JLFET and nanowire (NW) JLFET and shows an improved performance.

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“…The device has shown better performance characteristics, with improved linearity and distortion metrics making it suitable for low-power applications. Ferhati et al [17] reported a dual gate junctionless TFET that employs SiGe/germanium for the source/drain material and silicon for the channel material. This innovative design yields a remarkable subthreshold swing of 42mV/decade and an exceptional I ON /I OFF ratio of 115dB.…”

Section: Introductionmentioning

confidence: 99%

Analytical modeling and doping optimization for enhanced analog performance in a Ge/Si interfaced nanowire MOSFET

et al. 2023

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This paper critically investigates the effect of doping on different device characteristics of a Ge/Si interfaced nanowire MOSFET (GSI-NWM) for analog performance enhancement. The doping of source, channel, and drain has a prominent effect on important device characteristics, which has been investigated through DC and AC analysis performed on the SILVACO TCAD simulator. A numerical computational-based simulation study has been used to investigate the modulation of various device characteristics, such as threshold voltage, cut-off frequency, subthreshold swing, MTPG, current ratio, channel resistance, and transconductance. The investigation revealed a strong dependence of most of these characteristics on the source, channel, and drain doping levels, providing valuable insights into device performance. Proper optimization in doping can significantly improve the performance of the device. A compact physics-based analytical model has been mathematically evaluated and proposed in this work, showing an excellent in-line agreement with the simulated results. This is a novel approach for improving the analog performance parameters of a nanowire MOSFET through doping optimization, which incorporates gate oxide stacking and germanium as a source material. In this work, the biosensing capability of the GSI-NWM has also been discussed and evaluated.

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The role of the Ge mole fraction in improving the performance of a nanoscale junctionless tunneling FET: concept and scaling capability

Cited by 24 publications

References 26 publications

Interface trap-induced radiofrequency and low-frequency noise analysis under temperature variation of a heterostacked source L-gate tunnel field effect transistor

Interface trap-induced radiofrequency and low-frequency noise analysis under temperature variation of a heterostacked source L-gate tunnel field effect transistor

Parameteric optimization of SiGe S/D NT JLFET using analytical modeling to improve L‐BTBT induced GIDL

Analytical modeling and doping optimization for enhanced analog performance in a Ge/Si interfaced nanowire MOSFET

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