The influence of the SiN cap process on the electromigration and stressvoiding performance of dual damascene Cu interconnects

Abstract

The influence of the SIN cap-layer deposition process including different pre-clean treatments on the electromigration (EM) and stressvoiding (SV) behavior of copper dual damascene metalli:rations has been studied. A rcmarkable trade-off between the EM and SV performance was revealed depcnding primarily on the pre-treatment beforc cap-layer deposition rather than the deposition process itself On the one hand an "aggressive" pre-treatment yields improved CdSiN-interface properties with higher electromigration failure times and activation energies (1.22 ... 1.26eV). On the other hand these pre-cleans were found to provoke stressvoiding failures because of the recovery of crystal defects induced in the hulk copper during the plasma treatment. The degree of microstructural damage and hence thc SV susceptibility was found to increase with the preclean intensity. In contrast, no SV risk is related to "less aggressive" pre-clean treatments since they are influencing only the copper surface. The crystal structure of the bulk remains unaffected and hence -in absence of any crystal recovery -no vacancies will be generated. However, these pre-cleans result in significantly lower EM performance with smaller failure times and activation energies (1.03 ... 1.06eV).The results illustrate the need to adjust the SIN cap-layer process parameters with respect to both EM & SV performance to meet the overall reliability requirements for these wear-out mechanisms: at the same time.

Model for the barrier diffusion into Cu interconnects at high temperatures

“…In order to prove this assumption, the diffusion length has been calculated using Eqs. (5) and (6) for different test temperatures and times. The results in Table 4 show that for example after 10 h anneal at T > 500°C or 100 h anneal at T > 450°C, the Ta diffusion length is sufficient to completely block Cu diffusion paths at the interface of the narrow line.…”

“…As the interface between SiN cap layer and interconnect is known [5] to exhibit weak adhesion and to be a fast diffusion path for Cu, it is the preferred site for fails. Accordingly, the early failure (type A) occurs in the region with the highest current density and weakest interface.…”

“…For the lifetime of Cu interconnects, the quality of interfaces, especially between the dielectric cap (e.g. SiN) or the Ta barrier and Cu has been shown to be important [5].…”

Grain Size And Cap Layer Effects On Electromigration Reliability Of Cu Interconnects: Experiments And Simulation

“…EM in Cu interconnects differs significantly from that in Al interconnects, in which a stable Al oxide layer passivates the top interface and grain boundaries are the fastest pathways [1][2] . However, for Cu interconnects, mass transport along the Cu/SiNx interface is faster than at grain boundaries due to the defects on that interface created by the CMP process before cap layer deposition [3][4][5][6] . Prior to the 65 nm node with line width exceeding 100 nm, the Cu damascene lines were commonly observed to have a bamboo-like grain structure and the Cu/SiNx interface diffusion dominated the mass transport.…”

Electromigration Cu mass flow in Cu interconnections

“…Early review articles [2] point out some of the more important features of Cu technology and considerable work has been done to explore the reliability of Cu wiring, mainly in the area of electromigration and Cu/dielectric interactions [3][4][5][6][7][8]. Resistance to electromigration failure caused by mass transport and void growth has been receiving increasing attention as the continuous reduction in minimum feature size is beginning to exacerbate certain failure modes and thus may limit the current available to circuit designers.…”