The Impact of Layout on Stress-Enhanced Transistor Performance

Moroz, Victor; Eneman, G.; Verheyen, Peter; Nouri, F.; Washington, L.; Smith, Lee; Jurczak, M.; Pramanik, Dipankar; Xu, X. B.

doi:10.1109/sispad.2005.201493

Cited by 36 publications

(20 citation statements)

References 3 publications

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“…Band structure changes when stress is introduced. Variation of band structure will cause changes of mobility [15], threshold voltage [16], and saturation velocity (v sat ) [17], which have strong impacts on device performance. Thus, in this work, these three device parameters are investigated.…”

Section: Model Architecture and Foundationsmentioning

confidence: 99%

A Two-Dimensional Analysis Method on STI-Aware Layout-Dependent Stress Effect

Tan

et al. 2012

IEEE Trans. Electron Devices

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Strain technology has become indispensable for present CMOS integrated circuits (ICs) as the feature size of transistor shrinks. In the meantime, stress-induced variation has also become an unavoidable problem. Unintentional stress, such as shallow trench isolation (STI)-induced stress, is one of the main variation sources and is strongly layout dependent. In this paper, a new 2-D layout-dependent STI stress model and related device parameter model are proposed. The stress model captures layout parameters along both the longitudinal direction and the transverse direction, based on which channel stress induced by STI is derived. Device parameters including threshold voltage, mobility, and saturation velocity are then modified according to several analytical models. The model can be integrated into standard CMOS IC design flow. By comparing with TCAD simulation and experiments with 65-nm process, it shows that the new model can give a better prediction accuracy than the original process design kit.

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Section: Model Architecture and Foundationsmentioning

confidence: 99%

A Two-Dimensional Analysis Method on STI-Aware Layout-Dependent Stress Effect

Tan

et al. 2012

IEEE Trans. Electron Devices

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“…The accuracy of FEM based stress and mobility model are validated by 3D FEM device simulation [11], as shown in Fig. 6.…”

Section: A Mobility Variation Modelingmentioning

confidence: 99%

“…6. Variation of the mobility versus distance to TSV from modeled data and 3D device simulation [11]. stress on threshold voltage.…”

Section: B Threshold Voltage Variation Modelingmentioning

confidence: 99%

Methodology for analysis of TSV stress induced transistor variation and circuit performance

Chang²,

Zuo³

et al. 2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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Abstract-As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal mismatch between TSVs and the silicon bulk arising during wafer fabrication and 3D integration, is a key constraint. In this work, we propose a complete flow to characterize the influence of TSV stress on transistor and circuit performance. First, we analyze the thermal stress contour near the silicon surface with single and multiple TSVs through both finite element analysis (FEA) and linear superposition methods. Then, the biaxial stress is converted to mobility and threshold voltage variations depending on transistor type and geometric relation between TSVs and transistors. Next, we propose an efficient algorithm to calculate circuit variation corresponding to TSV stress based on a grid partition approach. Finally, we discuss a TSV pattern optimization strategy, and employ a series of 17-stage ring oscillators using 40 nm CMOS technology as a test case for the proposed approach.

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“…The stress effects affect model parameters such as the effective mobility µ ef f , the velocity saturation V sat and the threshold voltage V th [17], [18], [19]. To reflect the influence of SA ef f and SB ef f , the parameter "α" is defined as follows:…”

Section: Stress Effect Parameter Computation 1) the Stress Effectsmentioning

confidence: 99%

A Python-based layout-aware analog design methodology for nanometric technologies

Youssef

Javid

Dupuis

et al. 2011

2011 IEEE 6th International Design and Test Workshop (IDT)

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Abstract-This paper presents a methodology for procedural layout-aware design for nanometric technologies. A Python-based layout generation tool generates different layout styles for the same basic analog building blocks. Moreover, layout dependent parasitic parameters such as stress effects are easily computed and compared for different layout styles. The procedural layout description is written using a Python API that ensures layout portability over different technologies. A main focus is on how the layout generation tool addresses both geometric and parasiticaware electrical synthesis. This is made possible through an internal loop that links circularly both the sizing phase and the layout generation phase. The proposed design methodology assists the analog designer in exploring electrical and physical trade-offs. At the end, we present synthesis and characterization results that prove the effectiveness and speed of the proposed methodology.

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The Impact of Layout on Stress-Enhanced Transistor Performance

Cited by 36 publications

References 3 publications

A Two-Dimensional Analysis Method on STI-Aware Layout-Dependent Stress Effect

A Two-Dimensional Analysis Method on STI-Aware Layout-Dependent Stress Effect

Methodology for analysis of TSV stress induced transistor variation and circuit performance

A Python-based layout-aware analog design methodology for nanometric technologies

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