Abstract-As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal mismatch between TSVs and the silicon bulk arising during wafer fabrication and 3D integration, is a key constraint. In this work, we propose a complete flow to characterize the influence of TSV stress on transistor and circuit performance. First, we analyze the thermal stress contour near the silicon surface with single and multiple TSVs through both finite element analysis (FEA) and linear superposition methods. Then, the biaxial stress is converted to mobility and threshold voltage variations depending on transistor type and geometric relation between TSVs and transistors. Next, we propose an efficient algorithm to calculate circuit variation corresponding to TSV stress based on a grid partition approach. Finally, we discuss a TSV pattern optimization strategy, and employ a series of 17-stage ring oscillators using 40 nm CMOS technology as a test case for the proposed approach.
Abstract-Advanced CMOS processes need new methodologies to extract, characterize and model process variations and their sources. Most prior studies have focused on understanding the effect of local layout features on transistor performance; limited work has been done to characterize medium-range (≈ 10µm to 2mm) pattern density effects. We propose a new methodology to extract the radius of influence, or the range of neighboring layout that should be taken into account in determining transistor characteristics, for shallow trench isolation (STI) and polysilicon pattern density. A test chip, with 130k devices under test (DUTs) and step-like pattern density layout changes, is designed in 65nm bulk CMOS technology as a case study. The extraction result of the measured data suggests that the local layout geometry, within the DUT cell size of 6µm x 8µm, is the dominant contributor to systematic device variation. Across-die medium-range layout pattern densities are found to have a statistically significant and detectable effect, but this effect is small and contributes only 2-5% of the total variation in this technology.
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