Abstract:Abstract-Advanced CMOS processes need new methodologies to extract, characterize and model process variations and their sources. Most prior studies have focused on understanding the effect of local layout features on transistor performance; limited work has been done to characterize medium-range (≈ 10µm to 2mm) pattern density effects. We propose a new methodology to extract the radius of influence, or the range of neighboring layout that should be taken into account in determining transistor characteristics, … Show more
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