Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements

Extreme ultraviolet lithography and three dimensional integrated circuit—A review

“…In the last few years, several pre-bond test strategies were proposed such as built-in self test (BIST) structure, 67,69,70 scan switch network (SSN) structure, 71 and vertically addressed test structures (VATS). 72 Design rules play a key role in the physical design of 3D ICs. The introduction of new design rules is necessary for 3D IC design.…”