Test Challenges for 3D Integrated Circuits

Lee, H.-H.S.; Chakrabarty, Krishnendu

doi:10.1109/mdt.2009.125

Cited by 268 publications

(35 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Tester probe access for wafers is significantly more challenging in 3D chips than in 2D chips due to structures such as micro-bumps, which are too small, too dense and too numerous. New defects emerge for 3D chips due to processing steps that did not exist in 2D chips, e.g., wafer thinning, alignment and bonding [100]. Micro-bumps in 3D chips are susceptible to open/bridging defects [101].…”

Section: From 2d To 3d Chip Testingmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

show abstract

Section: From 2d To 3d Chip Testingmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

show abstract

“…The ICs are fabricated by stacking dies that are connected with Through Silicon Vias (TSVs) and micro solder bumps [2].…”

Section: Introductionmentioning

confidence: 99%

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

Ashikin

Hashizume

Yotsuyanagi

et al. 2018

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARY A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation.

show abstract

“…In comparison to testing of 2D ICs, 3D SICs introduce many new challenges for testing. The testing of 3D ICs has been considered as the number one challenge in research in 2009 [16]. Several researchers are still concentrating to make a breakthrough in this area [17]- [27].…”

Section: Introductionmentioning

confidence: 99%

Optimal stacking of SOCs in a 3D-SIC for post-bond testing

Pradhan

Giri

Rahaman

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

View full text Add to dashboard Cite

3D IC testing is one of the major concern in the semiconductor industry today. Multiple subsequent testing of partial stack during 3D assembly is required due to the die stacking steps of thinning, alignment and bonding. In this paper we address the problem of minimizing the total time of partial stack and complete stack testing. We analyze how the stacking sequence of different System-on-Chips (SOCs) in a 3D Stacked Integrated Circuit (SIC) affects the total test time. We propose an algorithm to find this stacking sequence to achieve the minimum test time. Our algorithm is run on ITC'02 benchmarks and the results are shown.Index Terms-Three-dimensional integration, through silicon via, test access mechanism, system-on-a-chip (SOC)

show abstract

Test Challenges for 3D Integrated Circuits

Cited by 268 publications

References 6 publications

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

Optimal stacking of SOCs in a 3D-SIC for post-bond testing

Contact Info

Product

Resources

About