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Scan chains are widely used to improve the testability of integrated circuits(ICs) and it is a major issue in circuit testing to optimize test overheads like area, delay and power. Previous work on scan chain design methodology for three-dimensional (3D) integrated circuits have been proposed for wire length optimization only. This paper has presented a Genetic Algorithm(GA) based formulation to provide a trade-off between delay and power optimization in scan chain reordering to come up with the ordering of flip-flops on the chain based upon a weighted cost function of delay and power consumption metrics. It has been observed that maximum improvement in power consumption is obtained as 53.78% for ISCAS89 benchmark circuits compared to unordered scan chain.

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