Scan Flip-Flop Ordering with Delay and Power Minimization during Testing

SoC Test Applications Using ACO metaheuristic

“…All the experiments were carried out for 100 ant-cycles and averaged over 10 trials. Tables 3 and 4 include the comparison of the proposed method with previous works [Jelodar, M. S. et al, 2006;Giri, C. et al 2005] using R-filled and MT-filled test vectors, respectively, in terms of the transition reduction rates during scan testing. As can be seen in Table 3 and 4, the proposed method gave 14% to 42% power reduction for R-filled test vectors and 19% to 84% power reduction for MT-filled test vectors.…”

“…Scan cell ordering methods have been proposed to reduce the switching activity in a scan-chain during scan test. Genetic algorithm (GA) is used to determine an optimized scan cell order [Jelodar, M. S. et al, 2006;Giri, C. et al, 2005]. However, the power reduction rate of these methods decreases as the number of scan-cells increases.…”

Scan Chain Design Targeting Dual Power and Delay Optimization for 3D Integrated Circuit

“…For estimating the power consumption we have considered the number of transitions within the flip-flop scan chain while the test vectors are scanned in, and output responses scanned out. The number of transitions caused by a test vector/response for a scan-in/scan-out is given by [5] T ransitions = (Size of Chain − P osition of T ransition) ... (2) where Size of chain is the number of flip-flops in the scan chain and Position of Transition is indexed from the least significant bit(LSB) for the input vectors, and from the most significant bit(MSB) for the responses. Transitions also Circuit Under Test (CUT) T otal T ransitions = (Size of Chain − P osition of T ransition) + size of Chain × Clashes ... (3) We have formed the scan chain in such a way that delay can be minimized, which in turn reduces the power consumption.…”

“…In our problem we have taken the fitness function as the weighted sum of both normalized value of delay and total number of transitions. This can be represented as Fitness = w × Normalized total transitions + (1-w) × Normalized delay (5) where Normalized total transitions = Total transitions/Maximum total transitions (6) and…”

“…Intensive research works have also been done to minimize power and delay separately using scan cell ordering in 2D chips. Though in [5] authors proposed a GA based scheme to optimize delay and power together, to the best of our knowledge, there is no prior work on the study of the dual minimization for 3D chips. In this paper, we have investigated a GA based formulation of the dual minimization of Delay and Power in three dimensional integrated circuit (3D ICs).…”