Scan Chain Design Targeting Dual Power and Delay Optimization for 3D Integrated Circuit

Abstract

Scan chains are widely used to improve the testability of integrated circuits(ICs) and it is a major issue in circuit testing to optimize test overheads like area, delay and power. Previous work on scan chain design methodology for three-dimensional (3D) integrated circuits have been proposed for wire length optimization only. This paper has presented a Genetic Algorithm(GA) based formulation to provide a trade-off between delay and power optimization in scan chain reordering to come up with the ordering of flip-flops on the chain based upon a weighted cost function of delay and power consumption metrics. It has been observed that maximum improvement in power consumption is obtained as 53.78% for ISCAS89 benchmark circuits compared to unordered scan chain.

Approach of genetic algorithm for power‐aware testing of 3D IC

“…If we consider that whatever be the partitions, the power requirement should not exceed certain power limit P max then the problem becomes further complex. Thus, as basically the problem of optimisation in the testing of VLSI circuits is a complex problem, several researchers tried to get the solution using GAs [32,[38][39][40].…”

“…A number of cores in SOCs d695, p22810, p34392 and p93791 are 10, 28, 19 and 32, respectively. For each SOC, the TAM widths chosen have seven instances 16,24,32,40,48,56 and 64. Columns 3, 4, 5 and 6 depict TSV limits in a 3D partition as reported in [31][32][33][34], while our work considering the partitions, B ≤ 4 and B ≤ 8 for Columns 7 and 8 depict the TSV limit.…”

Optimisation of test architecture in three‐dimensional stacked integrated circuits for partial stack/complete stack using hard system‐on‐chips

“…3D SIC testing has been a recent field of research. In spite of several benefits, testing of the 3D SIC suffers from great challenges [8] and various works have been reported on testing of 3D SICs [6, 7, 9–18] In [10], the authors proposed the optimisation of scan chain length along with scan power using the genetic algorithmic approach for 3D SOCs. TAM design for 3D SOCs using ILP is described in [11].…”

“…However, the limitation of the work proposed in [17] is that it does not consider multiple test insertions for testing the partial stacks. An optimisation method has been addressed in [6, 7] for minimising the test time of a 3D SIC, either for the final stack test or for any number of multiple test insertions during bonding. A drawback of this approach is that for a set of dies tested in parallel, the test pins of the dies are blocked until all the dies are tested.…”

“…Test architecture optimisation of 3D SICs can be addressed in two different scenarios where the test architecture for the die‐level wrapper is either fixed or can be changed. With respect to these two aspects, the dies can be soft, hard or firm [6].…”