Approach of genetic algorithm for power‐aware testing of 3D IC

Abstract

The interconnect between the cores of System-on-Chip (SOC) degrades the circuit performance by contributing to circuit delay and power consumption. To reduce this problem, SOC-based three-dimensional (3D) integrated circuit (IC) technology as a promising solution where multiple layers are stacked together decreasing the length of interconnect. However, 3D IC invites some new problems including more complexity in test generation. Testing of 3D IC requires test access architecture called Test Access Mechanism (TAM) for the purpose of transport of test stimuli to the cores placed in different layers. During testing due to increasing switching activity, any circuit demands higher power consumption and it becomes more acute for 3D IC. Moreover, testing of 3D ICs has other constraints. In this study, the authors address the issue of 3D IC testing using genetic algorithm-based approach to decrease test time. At first, available TAM width is partitioned into some fixed groups and they have to find partitioning of TAM and distribution of cores among layers with a goal to decrease test time. Next, they do the same considering, variable partitions with or without certain power limits. Experimental results establish the efficacy of the authors' method.

Power-Aware Bus Encoding Techniques For I/O and Data Buses: An Embedded System Analysis

“…By integrating the SOC system with various types of flash memory, I/O modules, power sources, and clock oscillators, a system developer can simply develop a complete mobile system. [5] [6]. The use of off-the-shelf standard components decreases overall system costs, shortens the development period, and speeds up product launch.…”