Temperature-aware microarchitecture

Task scheduling for multicore processors typically has aimed at higher throughput and lower power consumption, but the lifetime reliability may be harmed if negative bias temperature instability is not considered together. In this letter, a task scheduling which extends lifetime is proposed. Cores are given the chance to recover as long as performance is not degraded. The degradation simulator shows that the proposed scheduling improves the lifetime of a multicore processor by up to 36% over the existing task scheduling.

Section: Methodsmentioning

confidence: 99%

Recovery-enhancing task scheduling for multicore processors under NBTI impact

Hong

Lim

Kang

2014

“…3 illustrates the percentage of sampling points that the temperatures of one or more cores exceed the threshold temperature, 85℃. Although the number of cores is the smallest, the percentages are the highest in 8×8 IEICE Electronics Express, Vol.10, No.14, [1][2][3][4][5][6] many-core platforms since almost every core always works. DTM and TA result in the similar efficiency in the management of peak temperature, while keeping the percentage of temperature violations under 1%.…”

Section: Methodsmentioning

confidence: 99%

“…Once AVS is completed, the thermal characteristics of cores can be known. HotSpot [4] is used for the steady state temperature simulations. We assume that every core runs at the maximum frequency without any idle time.…”

Section: Process Variations and Avsmentioning

confidence: 99%

Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations

Hong

Lim

et al. 2013

Process variations yield the asymmetry on core performance in many-core processors. Adaptive voltage scaling can hide the variations, but that results in the different thermal characteristics of cores. By using the thermal characteristics, the efficiency of energy optimization and temperature management can be improved. Experiments showed that the proposed dynamic voltage frequency scaling consumes up to 25.2% less energy than the existing thermal management technique while remaining the ratio of peak temperature violations under 1%.

“…To obtain the peak temperature of the chip, the thermal model in HotSpot [5] is introduced in our method. This model is built as …”

Section: Optimization Modelmentioning

confidence: 99%

3D Networks-on-Chip mapping targeting minimum signal TSVs

Ding

Yang

et al. 2013

Abstract:The sharply increased complexity of multi-core systems has motivated the architecture of Networks-on-Chip (NoC) to evolve from 2D to 3D. With the objective of optimizing 3D NoC system for specific applications, a new mapping scheme with the goal of reducing signal TSVs and peak temperature is proposed in this paper. The interlayer communication is optimized, which facilitates reduction of signal TSVs. What's more, the peak temperature is limited by placing IP cores with high power on the layer close to the heat sink. Experimental results indicate that the number of signal TSVs is decreased and that tradeoffs can be made between the number of signal TSVs and peak temperature.