Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations

Self Cite

Stacking core layers is emerging as an alternative for future high performance computing, but thermal problems have to be tackled first. When adaptive voltage scaling is adopted to hide the growing variation in the performance of cores, as a result, heat generation of each core varies. By exploiting the static thermal characteristics, the efficiency of dynamic thermal management can be improved. The proposed thermal management reduces the energy consumption by up to 30.02% compared with existing techniques, while keeping the ratio of temperature violations around 1%.

Section: D Multicore Architecture and Thermal Characteristicsmentioning

confidence: 99%

Dynamic thermal management for 3D multicore processors under process variations

Hong

Lim

et al. 2013

Self Cite

“…The theoretical concept and design issues of optimal low power limits has strong face validity in recent publications such as; thermal aware dynamic voltage frequency scaling for energy consumption reduction [4], optimal combination of supply-body bias voltage to the core and memory for a real micro-controller chip [5], determining a set of supply-body bias voltage combinations to achieve the minimum energy consumption for a target frequency [6], analysis and determination of the best switching management strategy for dynamic set of operating environment in terms of process choices, circuit activity, and temperatures [7], an architecture based on the fully depleted silicon on insulator (FD-SOI) process technology for server operation near threshold region [8], standby leakage power consumption using the body bias and pin reordering technique for nanometer-scale CMOS circuits [9], finally, Adaptive supply and body voltage control for ultra-low power microprocessors using 22-nm technology model with considerable improvement in power and temperatures [10].…”

Section: Introductionmentioning

confidence: 99%

Microprocessors optimal power dissipation using combined threshold hopping and voltage scaling

Sulaiman

Hamarash

İbrahim

2017

The rapid growth in microprocessor's performance increases the power consumption significantly, resulting in rising microprocessor and system temperatures. High temperatures and eminent thermal variations of processors create severe challenges in system reliability, and cooling costs. Therefore, power and thermal management have become prominent issues of portable computer systems. Dynamic threshold hopping and supply voltage scaling (DTSVS) is an effective low-power design technique for reducing dissipated power. The technique adjusts the body bias (V BB ) or threshold voltage (V th ) and, correspondingly, the supply voltage (V dd ) adaptively in order to obtain a minimum power consumption and extend the processor's lifetime on a revolutionary scale. In this study, the optimal simultaneous combination set of the threshold and supply voltage (V th -V dd ) scaling is proposed to reduce power dissipation in the core of high-performance portable processors. Analysis and SPICE simulations are used to evaluate the presented theoretical basics and fundamentals. To ensure optimal V th -V dd sets; Particle Swarm Optimization (PSO) algorithm and Pareto Front (PF) solution are used. Both theoretical and simulation results show that, optimal amount of power consumption reduction has been obtained for different temperatures and workload environments.

“…V dd scaling requires a reduction in threshold voltage (V th ) and consequently increasing leakage power exponentially. In order to ensuring low power operation for efficient power and temperature aware design, finding optimal combination set of V dd and possibly body bias voltages (V BB ) that ensures the required performance of the portable processors is compulsory [1].…”

Section: Introductionmentioning

confidence: 99%

Adaptive supply and body voltage control for ultra-low power microprocessors

Sulaiman

Hamarash

İbrahim

2017

Power dissipation is a dominant aspect that limits the performance of microprocessors. In this work adaptive supply and body voltage control is used by applying optimum V dd and NMOS-PMOS body bias voltages (V BB-N & V BB-P ) to the microprocessor unit, which compensate the threshold voltage and clock frequency for ultra-low power design. SPICE simulation measurements on a 22-nm technology are used to evaluate the theoretical basics and fundamentals. The results show that, optimal amount of power consumption and temperature reduction have been obtained for different workload and simulation environments.