This paper proposes a pattern partitioning algorithm that maps multiple target patterns onto homogeneous memory-based string matchers. The proposed algorithm adopts the greedy search based on lexicographical sorting. By mapping as many target patterns as possible onto each string matcher, the memory requirements are greatly reduced.
This paper presents for hardware-based parallel pattern matching scheme that adopts heterogeneous bit-split string matchers for deep packet inspection (DPI) devices. Considering the pattern lengths, a set of target patterns is partitioned into two subsets for short and long patterns. By adopting the appropriate bit-split string matcher types for the two subsets, the memory requirements can be optimized for the bit-split parallel pattern matching engine. Experimental results show that the total memory requirements decrease by 39.40% and 20.52%, in comparison with the existing bit-split pattern matching approaches.
Process variations yield the asymmetry on core performance in many-core processors. Adaptive voltage scaling can hide the variations, but that results in the different thermal characteristics of cores. By using the thermal characteristics, the efficiency of energy optimization and temperature management can be improved. Experiments showed that the proposed dynamic voltage frequency scaling consumes up to 25.2% less energy than the existing thermal management technique while remaining the ratio of peak temperature violations under 1%.
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