A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection

Kim, Hyun‐Jin; Hong, Hyejeong; Baek, Dongmyoung; Ahn, Jin Ho; Kang, Sungho

doi:10.1587/elex.7.377

Cited by 6 publications

(13 citation statements)

References 5 publications

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“…Each category is used to make a DFA, it ignores the pattern set situation which initial characters of patterns is distributing sparsely. [27] consider the pattern lengths, partitioning the target pattern set into two subsets respectively for short and long patterns. For the bit-split parallel pattern matching engine, it is required to optimize the memory overhead to suit the proper bit-split string matcher types for the two subsets.…”

Section: Initial Charactermentioning

confidence: 99%

A Parallel Algorithm of Multiple String Matching Based on Set-Partition in Multi-core Architecture

Liu¹,

Li²,

Sun³

2016

IJSIA

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Section: Initial Charactermentioning

confidence: 99%

A Parallel Algorithm of Multiple String Matching Based on Set-Partition in Multi-core Architecture

Liu¹,

Li²,

Sun³

2016

IJSIA

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“…Several approaches to reduce the memory requirements for storing match vectors were proposed. In [ 10 ], the architecture with heterogeneous string matchers is adopted to enhance the efficiency of memory usage for mapping target patterns with various lengths. In [ 10 ], for the patterns with short pattern lengths, the FSM tile with a small number of states and PMVs is adopted.…”

Section: Previous Workmentioning

confidence: 99%

“…In [ 10 ], the architecture with heterogeneous string matchers is adopted to enhance the efficiency of memory usage for mapping target patterns with various lengths. In [ 10 ], for the patterns with short pattern lengths, the FSM tile with a small number of states and PMVs is adopted. On the other hand, for the patterns with long pattern lengths, a large number of states and PMVs is adopted.…”

Section: Previous Workmentioning

confidence: 99%

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A Memory-Efficient Deterministic Finite Automaton-Based Bit-Split String Matching Scheme Using Pattern Uniqueness in Deep Packet Inspection

Kim

Choi

2015

PLoS ONE

Self Cite

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This paper proposes a memory-efficient bit-split string matching scheme for deep packet inspection (DPI). When the number of target patterns becomes large, the memory requirements of the string matching engine become a critical issue. The proposed string matching scheme reduces the memory requirements using the uniqueness of the target patterns in the deterministic finite automaton (DFA)-based bit-split string matching. The pattern grouping extracts a set of unique patterns from the target patterns. In the set of unique patterns, a pattern is not the suffix of any other patterns. Therefore, in the DFA constructed with the set of unique patterns, when only one pattern can be matched in an output state. In the bit-split string matching, multiple finite-state machine (FSM) tiles with several input bit groups are adopted in order to reduce the number of stored state transitions. However, the memory requirements for storing the matching vectors can be large because each bit in the matching vector is used to identify whether its own pattern is matched or not. In our research, the proposed pattern grouping is applied to the multiple FSM tiles in the bit-split string matching. For the set of unique patterns, the memory-based bit-split string matching engine stores only the pattern match index for each state to indicate the match with its own unique pattern. Therefore, the memory requirements are significantly decreased by not storing the matching vectors in the string matchers for the set of unique patterns. The experimental results show that the proposed string matching scheme can reduce the storage cost significantly compared to the previous bit-split string matching methods.

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“…In a PHM computing system, a processor executes all tasks at the same speed, regardless of the type of each task. On the other hand, in a THM computing system, how fast a processor executes a task depends on whether the heterogeneous processor architecture matches the task requirements and memory features [3]. We use a THM computing system to balance the tasks of a multi-core processor.…”

Section: Introductionmentioning

confidence: 99%

A task-based multi-core allocation mechanism for packet acceleration

Guo

Liu

et al. 2018

IEICE Electron. Express

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Task allocation is a traditional and complicated problem for a system with many peripherals. Normal allocation methodology focuses on fuzzy data transfer but is unable to analyze some specific experimental statistics and does not improve system performance. Data Director (DD) is an innovative packet-based manager, is comprised of Data Index (DI) and Packet Direct Memory Access (PDMA) and realizes the enhanced data transfer in a complex system. This paper presents an improved task allocation model to enhance data transfer in a task-based model with three different allocation methodologies. The experimental results for the optimization allocations show that the proposed methodologies reduce the delay of transfer differently due to the schedule costs in these cases.

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A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection

Cited by 6 publications

References 5 publications

A Parallel Algorithm of Multiple String Matching Based on Set-Partition in Multi-core Architecture

A Parallel Algorithm of Multiple String Matching Based on Set-Partition in Multi-core Architecture

A Memory-Efficient Deterministic Finite Automaton-Based Bit-Split String Matching Scheme Using Pattern Uniqueness in Deep Packet Inspection

A task-based multi-core allocation mechanism for packet acceleration

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