3D Networks-on-Chip mapping targeting minimum signal TSVs

Abstract

Abstract:The sharply increased complexity of multi-core systems has motivated the architecture of Networks-on-Chip (NoC) to evolve from 2D to 3D. With the objective of optimizing 3D NoC system for specific applications, a new mapping scheme with the goal of reducing signal TSVs and peak temperature is proposed in this paper. The interlayer communication is optimized, which facilitates reduction of signal TSVs. What's more, the peak temperature is limited by placing IP cores with high power on the layer close to the heat sink. Experimental results indicate that the number of signal TSVs is decreased and that tradeoffs can be made between the number of signal TSVs and peak temperature.

3D NoC Low-Power Mapping Optimization Based on Improved Genetic Algorithm

“…The simulated annealing algorithm overcomes the poor local optimization ability of the traditional genetic algorithm and its premature phenomenon. Combining it with the traditional genetic algorithm will better exert the global optimization ability of the traditional genetic algorithm and the local optimization ability of the simulated annealing algorithm [25].…”