Tellurium doping of InGaP for tunnel junction applications in triple junction solar cells

Heavily tellurium doped n-type InGaAs grown by MOCVD on 300 mm Si wafers

“…In 0.53 Ga 0.47 As layer [15,16,18]. A high concentration of Te can cause strain relaxation, as reported in Figure 7, where the high resolution XRD omega-2theta scan of the SIMS sample shows an extra peak shifted -865 arcsec from the reference InP peak.…”

“…The influence of growth temperature on electron concentration and activation efficiency is shown in Figure 1b. As previously reported [11,14], the carrier concentration at the saturation condition increases as the growth temperature decreases: at 500 °C N d increased to 8 x 10 19 Te is known to have surfactant properties: it segregates at the growth front and affects the surface energy and the surface kinetic processes [13][14][15][16]. It has been reported that Te influences the step bunching of GaAs (001) vicinal surfaces and improves the surface morphology by preferentially attaching at step edges and reducing step height [13].…”

“…However, increasing the flow 50 times leads only to a small increase in dopant concentration, which goes from 5.8 to 10 x 10 19 cm -3 . This behavior can be explained by the volatile nature of tellurium: Te is known to have surfactant properties, and as such has the tendency to segregate at the step edges of the InGaAs growing surface [13,15,16]. Due to their high vapor pressure, Te adatoms tend to evaporate from the surface and their bulk incorporation efficiency decreases with increasing growth temperature [11,12,14]: the incorporation of tellurium reaches a saturation point which is a function of the growth temperature.…”

“…Tellurium surfactant properties, diffusion and memory effect have been extensively studied in doping of In x Ga (1-x) P system grown by MOCVD [15]. Optimized process conditions proved to be effective in growing Te-doped InGaP layers with sharp doping profiles for solar tunnel junctions [16].…”

“…Although the slow Te turn-off may not be important for the targeted VLSI S/D regrowth application, the slow turn-on will prevent the formation of an abrupt junction in the source/drain region, which is crucial for short channel devices [26]. A few strategies have been developed to minimize memory effect and achieve abrupt junctions, like pulsing DETe before the growth, for a sharper turn-on, or inserting a post growth bake after the doped layer to sublimate adsorbed DETe products from the wafer surface [16,18]. Tellurium incorporation also affects InGaAs composition.…”