Heavily tellurium doped n-type InGaAs grown by MOCVD on 300 mm Si wafers

Orzali, Tommaso; Vert, Alexey; Lee, Rinus T. P.; Norvilas, Aras; Huang, G. S.; Herman, Joshua; Hill, Richard J.; Rao, Satyavolu S. Papa

doi:10.1016/j.jcrysgro.2015.05.007

Cited by 14 publications

(13 citation statements)

References 24 publications

(31 reference statements)

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“…5b). The In 0.53 Ga 0.47 As carrier concentration N d was measured at room temperature with the Van der Pauw technique by alloying indium contacts to the InGaAs surface; in order to ensure adequate isolation from the buffer heterostructure during the Hall measurement, a highly resistive 300 nm InAlAs barrier layer lattice matched to InP was added underneath Sidoped InGaAs layers [17]. In Fig.…”

Section: N-moscap Structurementioning

confidence: 99%

“…The growth of uniform III-V films on blanket Si wafers in the top-down approach, on the other side, allows easier access to a wide range of device areas and metrology techniques, making it an extremely valuable approach to develop module level test structures and answer fundamental questions on large scale III-V on Si integration [17][18][19][20]. The main disadvantages of this approach are the high III-V film defect density, in the 10 8 -10 10 cm À 2 range, and their overall thickness, usually a few mm, which leads to the formation of additional defects and cracks in the structure, due to the thermal expansion coefficient mismatch between different layers.…”

Section: Introductionmentioning

confidence: 99%

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Growth and characterization of an In0.53Ga0.47As-based Metal-Oxide-Semiconductor Capacitor (MOSCAP) structure on 300mm on-axis Si (001) wafers by MOCVD

Orzali¹,

Vert²,

Kim³

et al. 2015

Journal of Crystal Growth

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Section: N-moscap Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Growth and characterization of an In0.53Ga0.47As-based Metal-Oxide-Semiconductor Capacitor (MOSCAP) structure on 300mm on-axis Si (001) wafers by MOCVD

Orzali¹,

Vert²,

Kim³

et al. 2015

Journal of Crystal Growth

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“…This result indicates that both group IV and group VI dopants are electrically limited at high doping levels due to some electrical compensation mechanism. Growth-based dopant incorporation methods have shown much higher (5 × 10 ) active concentrations 156 but these active concentrations are shown to be metastable in multiple studies 157 .…”

Section: (A) (B)mentioning

confidence: 99%

Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

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“…Te is known to have surfactant effects and improve crystalline growth quality in InGaAs 92 but Te also has a strong memory effect which may complicate the formation of abrupt junctions in epitaxially grown layers. 120 Processing conditions such as growth temperature and the ratio of group III to group V precursor overpressure also significantly effect post growth electrical activation. A survey of the growth doping literature suggests that lower growth temperatures improve the dopant activation in growth doped substrates.…”

Section: Strategies For Maximizing N-type Dopant Activation In Ingaasmentioning

confidence: 99%

Review—Dopant Selection Considerations and Equilibrium Thermal Processing Limits for n⁺-In_0.53Ga_0.47As

Lind

Aldridge

Hatem

et al. 2016

ECS J. Solid State Sci. Technol.

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An overview of various processing and dopant considerations for the creation of heavily-doped n-InGaAs is presented. A large body of experimental evidence and theoretical prediction point to dopant vacancy-complexing as the limiting mechanism for electrical activation in heavily Si doped InGaAs and GaAs. Dopant incorporation techniques which require thermal treatment steps to move dopants onto lattice sites like ion implantation and monolayer doping exhibit stable activation up to a limit of ≈1.5 × 1019 cm−3. Growth-based dopant incorporation methods have shown much higher (5 × 1019 cm−3) active concentrations but these activate concentrations are shown in multiple studies to be metastable. Other device specific process-flow constraints with respect to modern CMOS devices which may make some means of dopant incorporation method, or species selection more appropriate for a given application are also discussed.

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Heavily tellurium doped n-type InGaAs grown by MOCVD on 300 mm Si wafers

Cited by 14 publications

References 24 publications

Growth and characterization of an In0.53Ga0.47As-based Metal-Oxide-Semiconductor Capacitor (MOSCAP) structure on 300mm on-axis Si (001) wafers by MOCVD

Growth and characterization of an In0.53Ga0.47As-based Metal-Oxide-Semiconductor Capacitor (MOSCAP) structure on 300mm on-axis Si (001) wafers by MOCVD

Scaling Challenges for Advanced CMOS Devices

Review—Dopant Selection Considerations and Equilibrium Thermal Processing Limits for n⁺-In_0.53Ga_0.47As

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Heavily tellurium doped n-type InGaAs grown by MOCVD on 300 mm Si wafers

Cited by 14 publications

References 24 publications

Growth and characterization of an In0.53Ga0.47As-based Metal-Oxide-Semiconductor Capacitor (MOSCAP) structure on 300mm on-axis Si (001) wafers by MOCVD

Growth and characterization of an In0.53Ga0.47As-based Metal-Oxide-Semiconductor Capacitor (MOSCAP) structure on 300mm on-axis Si (001) wafers by MOCVD

Scaling Challenges for Advanced CMOS Devices

Review—Dopant Selection Considerations and Equilibrium Thermal Processing Limits for n+-In0.53Ga0.47As

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Review—Dopant Selection Considerations and Equilibrium Thermal Processing Limits for n⁺-In_0.53Ga_0.47As