The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

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Nickel germano-silicide ͑NiSiGe͒ contact was formed on silicon-germanium ͑Si 1−x Ge x or SiGe͒ epilayer with 26% Ge, grown on p-Si ͑100͒ substrate. We report the tuning of the effective Schottky barrier height ͑SBH͒ of holes at the NiSiGe/SiGe junction to sub-0.1 eV by the introduction of aluminum ͑Al͒ using ion implantation and its segregation at the NiSiGe/SiGe interface after germano-silicidation. The effective SBH decreases with increasing concentration of Al at the NiSiGe/SiGe interface. We demonstrate the achievement of one of the lowest reported hole SBHs for NiSiGe on SiGe of 0.068 eV, which is extremely promising for application in p-type metal oxide semiconductor field-effect transistors. The presence of Al does not affect the sheet resistance or the low-resistivity nickel mono-germano-silicide phase of the NiSiGe film. Our results indicate the possibility of an electric dipole at the NiSiGe/SiGe interface, introduced by Al atoms, which is responsible for the SBH modulation. Increase in thickness of nickel used for germano-silicidation increases the effective SBH. The increase in the Al implant dose reduces the effective SBH but degrades the SiGe epilayer by amorphizing it to a greater depth. Thus, a trade-off exists in choosing the Al implant dose and the nickel thickness needed to consume the amorphized SiGe for maximum device performance.Continuous scaling down of the size of complementary metal oxide semiconductor ͑CMOS͒ transistors has been a key enabler for the growth of the silicon integrated circuit industry, through drive current enhancement and cost reduction. However, as metal oxide semiconductor field-effect transistors ͑MOSFETs͒ become smaller, the parasitic series resistance ͑R SD ͒ starts to dominate over the channel resistance ͑R CH ͒. 1 This phenomenon became more severe with the introduction of strain in the channel to enhance carrier mobility at the 90 nm technology node. 1 For p-MOSFETs, it has been shown that the contact resistance ͑R C ͒ at the silicide/heavily doped-Si interface in the source/drain ͑S/D͒ region forms 36% of the total R SD . 2 With silicon-germanium ͑Si 1−x Ge x or SiGe͒ S/D currently being used in p-MOSFETs to incorporate uniaxial compressive strain in the channel, and nickel-based germano-silicide ͑NiSiGe͒ used as the salicide contact material, 3 there is a need to reduce the R C at the NiSiGe/SiGe interface. The lowest reported value for the effective hole Schottky barrier height ͑SBH͒ for NiSiGe on SiGe is ϳ0.2 eV. 4 With a need to achieve below 1 ϫ 10 −7 ⍀ cm 2 contact resistivity values, 5 extremely low SBH values are needed. Moreover, in multiple-gate field-effect transistors ͑or FinFETs͒ with narrow fin widths, R C easily dominates the total R SD , 6 further alleviating the need for lower SBH at the silicide/doped Si interface in S/D. Sulfur ͑S͒ and selenium ͑Se͒ segregation, nickel-aluminide-silicide, and the use of an interfacial oxide layer have been shown to reduce the effective SBH to sub-0.1 eV, but all of these techniques are only applicable for n-MO...

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Successful application of the silicide-like NixInGaAs phase for self-aligned source/drain contacts requires the formation of low-resistance ohmic contacts between the phase and underlying InGaAs. We report Ni-based contacts to InP-capped and uncapped n+- In0.53Ga0.47As (ND = 3 × 1019 cm−3) with a specific contact resistance (ρc) of 4.0 × 10−8 ± 7 × 10−9 Ω·cm2 and 4.6 × 10−8 ± 9 × 10−9 Ω·cm2, respectively, after annealing at 350 °C for 60 s. With an ammonium sulfide pre-metallization surface treatment, ρc is further reduced to 2.1 × 10−8 ± 2 × 10−9 Ω·cm2 and 1.8 × 10−8 ± 1 × 10−9 Ω·cm2 on epilayers with and without 10 nm InP caps, respectively. Transmission electron microscopy reveals that the ammonium sulfide surface treatment results in more complete elimination of the semiconductor's native oxide at the contact interface, which is responsible for a reduced contact resistance both before and after annealing.