TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET

Study of Silicon Body Thickness and Channel Length on SCEs and Electrical Performances of Underlapped GS-DG-MOSFET

“…The key performances such as Sub-threshold Slope (SS) [1], Threshold Voltage (VTH) and the Switching ratio (ION and IOFF ratio) [2] need to be analyzed at nanoscale devices. The Underlapped Gate-Stack Double-Gate MOSFET (U-GS-DG-MOSFET) has proven to be quite effective in reducing the SCEs among from numerous nanodevices proposed [3].…”

“…To overcome the tunneling effects, the gate insulators with dielectric (high-k) materials which can be replaced with of silicon dioxide (SiO2) [8]- [11]. To overcome the issue of scattering due to high-k dielectric material [12]- [14], the interfacing or padding layer is introduced known as Gate Stack (GS) which thereby enhance the electric field across the channel [5], [15], [2]. This paper reports on the SCEs and the electrical parameters of the U-GS-DG-MOSFET.…”

Influence of High-k Gate Dielectric on Nanoscale DG-MOSFET

“…This degradation is mainly caused by the fringing fields either from the gate to the source/drain regions or from the source/drain to the channel region which weakens the gate control [7]. But these shortcomings to some extent can be overcome by taking the gate stack (GS) configuration, i.e., high-k dielectrics over SiO 2 layer [8][9][10][11]. By taking a thick layer of dielectric material over a thin SiO 2 layer keeping EOT constant significantly reduces the gate tunnelling current.…”

Some Device Design Considerations to Enhance the Performance of DG-MOSFETs

“…To overcome these problems, various innovations in device structures have been researched and introduced. This has resulted in different structures with gate engineering, such as the Dual Material Gate (DM), Dual Insulator (DI) Gate, Gate Stack (GS), and channel engineering as graded channel (GC) [2,3]. Previously, Cheng et al [4] have shown the impact of high-k gate dielectrics on the device short channel parameters.…”

“…He discussed the physics and technology of these devices, and their advantages and disadvantages. In Sharma et al [3], different gate engineering and channel engineering under DG-MOSFET technology are discussed, and also a comparison of various parameters among DG-DM, DG-GC, DG-GS-DM and DG-GS-GC is highlighted. Aouaj et al [7] and Bendib et al [8] discussed the concept of GC and GS on the double gate platform.…”