Task mapping and mesh topology exploration for an FPGA-based network on chip

Abstract

International audienceTask mapping strategies on NoC (Network-on-Chip) have a huge impact on the timing performance and power consumption. So does the to-pology. In this paper, we describe the exploration flow of task mapping algorithms using different NoC mesh shapes. The flow is used to evaluate timing and energy consumption based on a NoC emulation platform. It is open to any task mapping algorithms and to any shapes of NoC mesh. A heterogeneous (PC and FPGA) platform is used to fully perform each step of the flow. The experiments demonstrate that the most appropriate task mapping strategy and the most suitable NoC shape strongly depend on the algorithm used. Depending on the timing latency results obtained and the FPGA resources used, the designer can select the appropriate task mapping strategy on the suitable shape in a short exploration time and with precise timing evaluation

Task Decomposition Exploration of Image Processing Applications on FPGA-Based NoC

“…It includes two stages: the first is to generate subtask graphs based on the analysis of the inherent parallelizability of the application. In the second stage, following the exploration flow proposed in [8], the subtask graphs generated in the first stage will be evaluated on the FPGA-based NoC emulation platform to shorten the evaluation cycle.…”

“…Depending on different task decomposition strategies, different subtask graphs are generated for the specific application. The evaluation of the subtask graphs based on the task mapping exploration flow [8] can provide abundant data about the timing delay results of these schemes. These data can help the designer to determine the most appropriate task decomposition scheme for the special application before implementing the application with real code (i.e.…”

Fault-Tolerant in Embedded Systems (MPSoC): Performance Estimation and Dynamic Migration Task

“…In [6], the authors proposes a design flow to explore mapping strategies and shape of the NoC network to improve synchronization performance and the power consumption, then for each step of the flow they used a heterogeneous platform (PC and FPGA) to fulfill them. The exploration flow is provided to help designers NoC to choose a technique appropriate mapping tasks on a NoC appropriate form for a particular application.…”

“…Fault tolerance approach for embedded systems multiprocessor (Multiprocessor System on Chip MPSoC), combines the results of a hybrid model (proposed by LIP2 laboratory, in [6]) and a technical fault tolerance that is based on the dynamic migration. This approach provides an effective solution to the current problems of modern embedded systems.…”

Dynamic data flow analysis for NoC based application synthesis

“…This algorithm gives very good results but does not scale well. Such limitations can be overcome by using faster algorithms but with poorest results [17].…”