Multiprocessor System on Chip (MPSoC) technology presents an interesting solution to reduce the computational time of complex applications such as multimedia applications. Implementing the new High Efficiency Video Coding (HEVC/h.265) codec on the MPSoC architecture becomes an interesting research point that can reduce its algorithmic complexity and resolve the real time constraints. The implementation consists of a set of steps that compose the Co-design flow of an embedded system design process. One of the first anf key steps of a Co-design flow is the modeling phase which allows designers to make best architectural choices in order to meet user requirements and platform constraints. Multimedia applications such as HEVC decoder are complex applications that demand increasing degrees of agility and flexibility. These applications are usually modeling by dataflow techniques. Several extensions with several schedules techniques of dataflow model of computation have been proposed to support dynamic behavior changes while preserving static analyzability. In this paper, the HEVC/h.265 video decoder is modeled with SADF based FSM in order to solve problems of placing and scheduling this application on an embedded architecture. In the modeling step, a high-level performance analysis is performed to find an optimal balance between the decoding efficiency and the implementation cost, thereby reducing the complexity of the system. The case study in this case works with the HEVC/h.265 decoder that runs on the Xilinx Zedboard platform, which offers a real environment of experimentation.
In recent years, computational requirements for embedded applications are increasing exponentially. This complexity, coupled with constantly evolving specifications, has forced designers to consider intrinsically flexible implementations. For this reason, heterogeneous multiprocessor architectural platforms are gaining prevalence for embedded systems. Deploying applications typical of multimedia domains is difficult, not only due to the heterogeneous parallelism in the platforms, but also due to the performance constraints that typify these systems. In this paradigm, the digital system-on-a-chip (SoC) platform-based design environment for shared memory multiple instructions multiple data (MIMD) architectures (Disydent) is used. The applicability of the Disydent design flow to systems in the multimedia domain is illustrated. The case studied consists in deploying a Motion JPEG decoder application onto a configurable prototype of a multiprocessor MIPS platform architecture.
Task migration has a great consideration is MPSoC design and implementation of embedded systems in order to improve performance related to optimizing execution time or reducing energy consumption. Multi-Processor Systems-on-Chip (MPSoC) are now the leading hardware platform featured in embedded systems. This chapter deals with the impact of task migration as an alternative to meet performance constraints in the design flow. The authors explain the different levels of the design process and propose a methodology to master the migration process at transaction level. This methodology uses some open source tools like SDF3 modified to provide performance estimation at transaction level. These results help the designer to choose the best hardware model in replacement of the previous software implementation of the task object of migration. Using the SDF3 tool, the authors model a multimedia application using SDF graphs. Secondly, they target an MPSoC platform. The authors take a performance constraint to achieve 25 frames per second.
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