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International audienceTask mapping strategies on NoC (Network-on-Chip) have a huge impact on the timing performance and power consumption. So does the to-pology. In this paper, we describe the exploration flow of task mapping algorithms using different NoC mesh shapes. The flow is used to evaluate timing and energy consumption based on a NoC emulation platform. It is open to any task mapping algorithms and to any shapes of NoC mesh. A heterogeneous (PC and FPGA) platform is used to fully perform each step of the flow. The experiments demonstrate that the most appropriate task mapping strategy and the most suitable NoC shape strongly depend on the algorithm used. Depending on the timing latency results obtained and the FPGA resources used, the designer can select the appropriate task mapping strategy on the suitable shape in a short exploration time and with precise timing evaluation

IC industry has made great progress in the recent years. However, restricted by the funds and budget, resources of IC design and test are imbalanced. This paper describes an architecture of Cloud-EDA Platform based on Cloud Computing, which is the most popular topic of the internet and IT industry for its high flexibility and low cost. According to the proposed architecture, we design the prototype of Cloud-EDA Platform and develop an application of test-pattern-conversion, which demonstrate that cloud computing can be combined with IC industry to enable ordinary users, app developers and EDA vendors to achieve a win-win-win result.

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