Generation of high speed CMOS multiplier-accumulators

Pang, Ke; Soong, Hong-Tie; Sexton, Ralph; Ang, Peng Hwa

doi:10.1109/iccd.1988.25694

Cited by 21 publications

(7 citation statements)

References 6 publications

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“…Although we are not comparing the same design (complex number multiplier) and the size of the mantissas differ (13 vs. 16 bit), the differences can be estimated. The best implementation of the reported 16 • integer multiplier-accumulator yields a result in 19.7 nS [17]. Our multiplier multiplies two complex numbers with 13-bit mantissas and yields a complex multiplication result in 20.8 nS in the same LSI 10K ASIC technology.…”

Section: Resultsmentioning

confidence: 93%

“…The advantage of our approach is due to the use of a better and optimized Wallace tree (using 4:2 adders) and also in optimization which is done across the Wallace tree and Final Adder (tuning the adder to the Wallace tree). We have not optimized the paths by p o w e r i n g the critical paths via buffering as it was done in [17]. However, powering the critical paths would give us an additional advantage in speed.…”

Section: Resultsmentioning

confidence: 95%

“…However, the basic findings and observations will still remain. We compared the results of our design with an ASIC implementation of a 16-bit multiplier-accumulator implemented in the LSI 10K ASIC technology [17]. Although we are not comparing the same design (complex number multiplier) and the size of the mantissas differ (13 vs. 16 bit), the differences can be estimated.…”

Section: Resultsmentioning

confidence: 99%

“…It was observed that they arrive sooner at the ends of the multiplier tree, while the signals in the middle of the tree arrive last [17]. The ideal situation would be to trim some of the delay from the middle of the tree and distribute it toward the ends.…”

Section: Signal Arrival Time In the Multipliermentioning

confidence: 97%

“…Such an approach has been first taken by K. Pang et al of LSI Logic Corporation in the implementation of their MACGEN tool. Their tool automatically generates optimized netlist and compact layout for multiplier-accumulator implementations [17].…”

Section: Signal Arrival Time In the Multipliermentioning

confidence: 99%

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An integrated multiplier for complex numbers

Oklobdzija

Villeger²,

Soulas³

1994

Journal of VLSI Signal Processing

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Abstract. In this article we consider a design of a multiplier for the multiplication of complex numbers. The complex numbers are packed into one 32-bit word. They are represented by two 13-bit parts with the same 6-bit exponent. Multiplication of complex numbers is examined from the perspectives of performance, complexity and silicon area. The design is unique and combines shared Booth encoding for the real and imaginary parts including only one combined modified Wallace tree of 4:2 adders for each part. The regular Wallace tree is compared with the tree of 4:2 adders. This design results in a more compact wiring structure and balanced delays resulting in a faster multiplier circuit. The number of adders used in the multiplier is also reduced. We consider VLSI CMOS technology and the relevant characteristics as they impact the implementation and performance.

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Section: Resultsmentioning

confidence: 93%

Section: Resultsmentioning

confidence: 95%

Section: Resultsmentioning

confidence: 99%

Section: Signal Arrival Time In the Multipliermentioning

confidence: 97%

Section: Signal Arrival Time In the Multipliermentioning

confidence: 99%

See 3 more Smart Citations

An integrated multiplier for complex numbers

Oklobdzija

Villeger²,

Soulas³

1994

Journal of VLSI Signal Processing

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High-performance VLSI multiplier with a new redundant binary coding

Huang

Wei

Chen

et al. 1991

J VLSI Sign Process Syst Sign Image Video Technol

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High speed merged array multiplication

Islam

Tamaru

1995

Journal of VLSI Signal Processing

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Multiplication-accumulation operations described by )--~k=0 Ak Bk represent the fundamental computation involved in many digital signal processing algorithms. For high speed signal processing, one obvious approach to realize the above computation in VLSI is to employ m discrete multipliers working in parallel. However, a more area efficient approach is offered by the merged multiplication technique [5]. But the principal drawback of the conventional merged technique is its longer latency than the former discrete approach. This work proposes a hardware algorithm for merged array multiplication which eliminates this drawback and achieves significant improvement in latency when compared with the conventional scheme for merged multiplication. The proposed algorithm utilizes multiple wave front computation as opposed to the traditional approach where computation in an array multiplier is carried out by a single wave front. The improvement in latency by the proposed approach is greater than 40% (for m > 2) when compared with a conventional approach to merged multiplication. The consequent cost in the form of additional requirement of VLSI area is found to be rather small. In this paper, we provide a thorough analytic discussion on the proposed algorithm and support it by experimental results.

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Generation of high speed CMOS multiplier-accumulators

Cited by 21 publications

References 6 publications

An integrated multiplier for complex numbers

An integrated multiplier for complex numbers

High-performance VLSI multiplier with a new redundant binary coding

High speed merged array multiplication

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