High-performance VLSI multiplier with a new redundant binary coding

Huang, Xiaoping; Wei, B.W.Y.; Chen, Honglu; Mao, Yu-Hai

doi:10.1007/bf00936901

Cited by 13 publications

(2 citation statements)

References 8 publications

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“…A similar encoding of the recoded digits using 3 bits was given in [22]. Only 5 of the 8 combinations of the r-cell outputs appear in this encoding.…”

Section: Proposed Modifications For the R-cells Andps-cellsmentioning

confidence: 99%

C-Testable modified-Booth multipliers

et al. 1996

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In this paper the testability of modified-Booth array multipliers for standard cells based design environments is examined for first time. In such cases the structure of the cells may be unknown, thus Cell Fault Model (CFM) is adopted. Two C-testable designs are proposed. A design for an Nx x Ny bits modified-Booth multiplier, which uses ripple carry addition at the last stage of the multiplication, is first proposed. The design requires the addition of only one extra primary input and 38 test vectors with respect to CFM. A second C-testable design is given using carry lookahead addition at the last stage which is the case of practical implementations of modified-Booth multipliers. Such a C-testable design using carry lookahead addition is for first time proposed in the open literature. This second design requires the addition of 4 extra primary inputs. One-level and two-levels carry lookahead adders, are considered. The C-testable design requires 61 test vectors for the former and 73 test vectors for the latter, respectively. The hardware and delay overheads imposed by both C-testable designs are very small and decrease when the size of the multiplier increases.

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“…A similar encoding of the recoded digits using 3 bits was given in [22]. Only 5 of the 8 combinations of the r-cell outputs appear in this encoding.…”

Section: Proposed Modifications For the R-cells Andps-cellsmentioning

confidence: 99%

C-Testable modified-Booth multipliers

et al. 1996

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“…The output of the multiplier is 40 bits. The coding of the signed-digit is the one discussed in [15] where designing the Booth encoders based on that coding reduces the number of levels in the tree by one.…”

Section: Multipliermentioning

confidence: 99%

A VLSI Design for Implementation of TransformDomain Adaptive Filters

1996

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A VLSI implementation of a dedicated digital signal processor is presented. The processor is tailored for efficient implementation of transform domain adaptive filters. It incorporates a butterfly processor which performs butterfly operation to implement the required transformation. It is also able to perform complex addition, subtraction and multiplication. The butterfly processor makes use of a redundant binary tree multiplier with a recently proposed coding of signed-digit numbers which reduces the number of levels in the tree by one. An on-chip read only memory holds the transformation coefficients. The contents of the ROM determine the type of transform. The processor incorporates an ALU to perform integer arithmetic, address calculations and implementation of circular memory scheme. For fastest accessibility, the essential variables of the algorithm are implemented in a register fire.

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